update 2020.1 vivado projects (#1057)

* update bitstreams to 2020.1

* include bit when generating xsa

.gitignore

@@ -27,6 +27,11 @@ thumbs.db
 build/
 sdcard/
 
+# Raw overlay files
+*.bit
+*.hwh
+*.xsa
+
 # Test failure outputs
 ######################
 tests/*.exp

boards/Pynq-Z1/base/build_bitstream.tcl

@@ -5,21 +5,27 @@ set design_name "base"
 open_project ./${overlay_name}/${overlay_name}.xpr
 open_bd_design ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd
 
-# Add top wrapper and xdc files
+# add top wrapper and xdc files
 make_wrapper -files [get_files ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top
 add_files -norecurse ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.v
 set_property top ${design_name}_wrapper [current_fileset]
 import_files -fileset constrs_1 -norecurse ./vivado/constraints/${overlay_name}.xdc
 update_compile_order -fileset sources_1
 
+# set platform property
+set_property platform.default_output_type "sd_card" [current_project]
+set_property platform.design_intent.embedded "true" [current_project]
+set_property platform.design_intent.server_managed "false" [current_project]
+set_property platform.design_intent.external_host "false" [current_project]
+set_property platform.design_intent.datacenter "false" [current_project]
+
 # call implement
 launch_runs impl_1 -to_step write_bitstream -jobs 4
 wait_on_run impl_1
 
-# This hardware definition file will be used for microblaze projects
-file mkdir ./${overlay_name}/${overlay_name}.sdk
-write_hwdef -force  -file ./${overlay_name}/${overlay_name}.sdk/${overlay_name}.hdf
-file copy -force ./${overlay_name}/${overlay_name}.sdk/${overlay_name}.hdf .
+# generate xsa
+write_hw_platform -include_bit -force ./${overlay_name}.xsa
+validate_hw_platform ./${overlay_name}.xsa
 
 # move and rename bitstream to final location
 file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ${overlay_name}.bit

boards/Pynq-Z2/base/build_base_ip.tcl → boards/Pynq-Z1/base/build_ip.tcl

@@ -21,7 +21,7 @@ foreach item $ip {
    set latency_flag 0
    while { [gets $fd line] >= 0 } {
 # Check whether the timing has been met
-    if [string match {+ Timing (ns): } $line]  { 
+    if [string match {+ Timing: } $line]  { 
       set timing_flag 1
       set latency_flag 0
       continue
@@ -38,17 +38,17 @@ foreach item $ip {
       }
     }
 # Check whether the II has been met
-    if [string match {+ Latency (clock cycles): } $line]  { 
+    if [string match {+ Latency: } $line]  { 
       set timing_flag 0
       set latency_flag 1
       continue
     }
     if {$latency_flag == 1} {
       if [regexp {[0-9]+} $line]  {
-        set interval [regexp -all -inline {[0-9]+} $line]
-        lassign $interval l iteration achieved target
+        set interval [regexp -all -inline {[0-9]*\.*[0-9]*} $line]
+        lassign $interval lc_min lc_max la_min la_max achieved target
         if {$achieved != $target} {
-            puts "ERROR: Achieved II $achieved != target $target for loop $l."
+            puts "ERROR: Achieved II $achieved != target $target."
             puts "ERROR: Revise $item to be compatible with Vivado_HLS."
             exit 1
         }
@@ -63,4 +63,4 @@ foreach item $ip {
    unset fd
 }
 cd $current_dir
-puts "HLS IP builds complete"
+puts "HLS IP builds complete"

boards/Pynq-Z1/base/makefile

@@ -1,13 +1,13 @@
 overlay_name := base
 design_name := base
 
-all: hls_ip block_design bitstream check_timing dsa
+all: hls_ip block_design bitstream check_timing
 	@echo
 	@tput setaf 2 ; echo "Built $(overlay_name) successfully!"; tput sgr0;
 	@echo
 
 hls_ip:
-	vivado -mode batch -source build_$(overlay_name)_ip.tcl -notrace
+	vivado -mode batch -source build_ip.tcl -notrace
 
 block_design:
 	vivado -mode batch -source $(overlay_name).tcl -notrace
@@ -16,10 +16,7 @@ bitstream:
 	vivado -mode batch -source build_bitstream.tcl -notrace
 
 check_timing:
-	vivado -mode batch -source check_$(overlay_name).tcl -notrace
-
-dsa:
-	vivado -mode batch -source build_$(overlay_name)_dsa.tcl -notrace
+	vivado -mode batch -source check_timing.tcl -notrace
 
 clean:
-	rm -rf $(overlay_name) *.jou *.log NA
+	rm -rf $(overlay_name) *.jou *.log NA .Xil

boards/Pynq-Z1/logictools/build_bitstream.tcl

@@ -12,14 +12,20 @@ set_property top ${design_name}_wrapper [current_fileset]
 import_files -fileset constrs_1 -norecurse ./vivado/constraints/${overlay_name}.xdc
 update_compile_order -fileset sources_1
 
+# set platform property
+set_property platform.default_output_type "sd_card" [current_project]
+set_property platform.design_intent.embedded "true" [current_project]
+set_property platform.design_intent.server_managed "false" [current_project]
+set_property platform.design_intent.external_host "false" [current_project]
+set_property platform.design_intent.datacenter "false" [current_project]
+
 # call implement
 launch_runs impl_1 -to_step write_bitstream -jobs 4
 wait_on_run impl_1
 
-# This hardware definition file will be used for microblaze projects
-file mkdir ./${overlay_name}/${overlay_name}.sdk
-write_hwdef -force  -file ./${overlay_name}/${overlay_name}.sdk/${overlay_name}.hdf
-file copy -force ./${overlay_name}/${overlay_name}.sdk/${overlay_name}.hdf .
+# generate xsa
+write_hw_platform -include_bit -force ./${overlay_name}.xsa
+validate_hw_platform ./${overlay_name}.xsa
 
 # move and rename bitstream to final location
 file copy -force ./${overlay_name}/${overlay_name}.runs/impl_1/${design_name}_wrapper.bit ${overlay_name}.bit

boards/Pynq-Z2/logictools/build_logictools_ip.tcl → boards/Pynq-Z1/logictools/build_ip.tcl

@@ -21,7 +21,7 @@ foreach item $ip {
    set latency_flag 0
    while { [gets $fd line] >= 0 } {
 # Check whether the timing has been met
-    if [string match {+ Timing (ns): } $line]  { 
+    if [string match {+ Timing: } $line]  { 
       set timing_flag 1
       set latency_flag 0
       continue
@@ -38,17 +38,17 @@ foreach item $ip {
       }
     }
 # Check whether the II has been met
-    if [string match {+ Latency (clock cycles): } $line]  { 
+    if [string match {+ Latency: } $line]  { 
       set timing_flag 0
       set latency_flag 1
       continue
     }
     if {$latency_flag == 1} {
       if [regexp {[0-9]+} $line]  {
-        set interval [regexp -all -inline {[0-9]+} $line]
-        lassign $interval l iteration achieved target
+        set interval [regexp -all -inline {[0-9]*\.*[0-9]*} $line]
+        lassign $interval lc_min lc_max la_min la_max achieved target
         if {$achieved != $target} {
-            puts "ERROR: Achieved II $achieved != target $target for loop $l."
+            puts "ERROR: Achieved II $achieved != target $target."
             puts "ERROR: Revise $item to be compatible with Vivado_HLS."
             exit 1
         }
@@ -63,4 +63,4 @@ foreach item $ip {
    unset fd
 }
 cd $current_dir
-puts "HLS IP builds complete"
+puts "HLS IP builds complete"