Update T-HEAD to XuanTie.

README.md

@@ -1,6 +1,6 @@
-# T-Head ISA extensions (Xthead*)
+# XuanTie ISA extensions (Xthead*)
 
-This repository contains the T-Head RISC-V ISA extensions (Xthead*) specifications.
+This repository contains the XuanTie RISC-V ISA extensions (Xthead*) specifications.
 
 ## Build instructions
 

docinfo.adoc

@@ -5,7 +5,7 @@ This specification is licensed under the Apache License, Version 2.0
 (Apache-2.0). The full license text is available at
 https://www.apache.org/licenses/LICENSE-2.0.
 
-Copyright 2022 T-Head Semiconductor Co., Ltd.
+Copyright 2024 Hangzhou C-SKY MicroSystems Co., Ltd.
 
 Copyright 2022 VRULL GmbH
 

intro.adoc

@@ -1,6 +1,6 @@
 == Introduction
 
-The T-Head extension collection was created to augment
+The Alibaba Damo Academy Xuantie extension collection was created to augment
 the RISC-V ISA by adding additional functionality
 to enable faster and more energy-efficient solutions.
 
@@ -15,13 +15,13 @@ The RISC-V ISA and its authors strongly advertise the ability
 to create vendor extensions. Dedicated encoding spaces ensure,
 that there are not conflicts with standard extensions.
 
-This document specifies the T-Head extension collection,
+This document specifies the XuanTie extension collection,
 a collection of vendor extensions that are implemented
-in many T-Head processors.
+in many XuanTie processors.
 
 === Overview
 
-The T-Head extension collection follows the principles of the RISC-V ISA.
+The XuanTie extension collection follows the principles of the RISC-V ISA.
 The collection consists of the following ISA extensions:
 
 * `XTheadSxStatus` provides a CSR to probe the availability of XThead* extensions.
@@ -42,7 +42,7 @@ The collection consists of the following ISA extensions:
 
 === Dependencies to standard extensions
 
-The T-Head extension collection is designed to be compatible
+The XuanTie extension collection is designed to be compatible
 with RISC-V's base integer instruction sets RV32I and RV64I.
 
 Some instructions are only available if the system's

xthead.adoc

@@ -1,8 +1,8 @@
 [[header]]
-:description: T-Head ISA extensions (Xthead*)
-:company: T-Head Semiconductor Co., Ltd
+:description: XuanTie ISA extensions (Xthead*)
+:company: Alibaba Damo Academy(Xuantie Team)
 include::revision.adoc-snippet[]
-:url-thead: https://www.t-head.cn
+:url-thead: https://www.xrvm.cn
 :doctype: book
 :preface-title: Preamble
 :colophon:
@@ -28,7 +28,7 @@ endif::[]
 :footnote:
 :xrefstyle: short
 
-= T-Head ISA extension specification (Xthead*)
+= XuanTie ISA extension specification (Xthead*)
 
 include::docinfo.adoc[]
 

xtheadsxstatus.adoc

@@ -1,11 +1,11 @@
 [#xtheadsxstatus]
-== T-Head extension status register for S-mode (XTheadSxStatus)
+== XuanTie extension status register for S-mode (XTheadSxStatus)
 
 [NOTE,caption=Frozen]
 The `XTheadSxStatus` extension is `stable`.
 
 The `XTheadSxStatus` ISA extension provides the `th.sxstatus` CSR that holds
-status information and allows to control T-Head custom extensions.
+status information and allows to control XuanTie custom extensions.
 
 Extension version: 1.0.
 

xtheadvector.adoc

@@ -1,5 +1,5 @@
 [#xtheadvector]
-== T-Head's vector extension (XTheadVector)
+== XuanTie's vector extension (XTheadVector)
 
 [NOTE,caption=Frozen]
 The `XTheadVector` extension is `stable`.
@@ -44,12 +44,12 @@ While similar to the `V` Extension v0.7.1, `XTheadVector` still exhibits some di
 
 The `XTheadVector` extension is available if and only if all of the following conditions are met:
 
-* The value of the `mvendor` CSR is `0x5b7` ('T-Head')
+* The value of the `mvendor` CSR is `0x5b7` ('XuanTie')
 * Bit 21 of the `misa` CSR is `1` ('V')
 * The value of the `mimpid` CSR is `0`
 
 These conditions not only reliably identify existing CPUs with `XTheadVector` (C906V, C920, and R920),
-but also ensure that future T-Head CPUs without `XTheadVector` won't be falsely detected (in this case `mimpid` won't be `0`).
+but also ensure that future XuanTie CPUs without `XTheadVector` won't be falsely detected (in this case `mimpid` won't be `0`).
 
 === Intrinsics