Add i64x2.bitmask to text

This was accepted into this proposal in #410.
WebAssembly · Jan 26, 2021 · 6ff10c8 · 6ff10c8
1 parent 194b993
commit 6ff10c8
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Showing 5 changed files with 6 additions and 1 deletion.
diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py
@@ -471,6 +471,7 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
     Instruction(r'\I32X4.\VMAX\K{\_s}', r'\hex{FD}~~184', r'[\V128~\V128] \to [\V128]', r'validation <valid-vbinop>', r'execution <exec-vbinop>', r'operator <op-imax_s>'),
     Instruction(r'\I32X4.\VMAX\K{\_u}', r'\hex{FD}~~185', r'[\V128~\V128] \to [\V128]', r'validation <valid-vbinop>', r'execution <exec-vbinop>', r'operator <op-imax_u>'),
     Instruction(r'\I64X2.\VNEG', r'\hex{FD}~~193', r'[\V128] \to [\V128]', r'validation <valid-vunop>', r'execution <exec-vunop>', r'operator <op-ineg>'),
+    Instruction(r'\I64x2.\BITMASK', r'\hex{FD}~~196', r'[\V128] \to [\I32]', r'validation <valid-simd-bitmask>', r'execution <exec-simd-bitmask>'),
     Instruction(r'\I64X2.\VSHL', r'\hex{FD}~~203', r'[\V128~\I32] \to [\V128]', r'validation <valid-vshiftop>', r'execution <exec-vshiftop>', r'operator <op-ishl>'),
     Instruction(r'\I64X2.\VSHR\K{\_s}', r'\hex{FD}~~204', r'[\V128~\I32] \to [\V128]', r'validation <valid-vshiftop>', r'execution <exec-vshiftop>', r'operator <op-ishr_s>'),
     Instruction(r'\I64X2.\VSHR\K{\_u}', r'\hex{FD}~~205', r'[\V128~\I32] \to [\V128]', r'validation <valid-vshiftop>', r'execution <exec-vshiftop>', r'operator <op-ishr_u>'),

diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst
@@ -419,6 +419,7 @@ Instruction                                  Binary Opcode          Type
 :math:`\I32X4.\VMAX\K{\_s}`                  :math:`\hex{FD}~~184`  :math:`[\V128~\V128] \to [\V128]`              :ref:`validation <validation <valid-vbinop>>`                :ref:`execution <execution <exec-vbinop>>`, :ref:`operator <operator <op-imax_s>>`      
 :math:`\I32X4.\VMAX\K{\_u}`                  :math:`\hex{FD}~~185`  :math:`[\V128~\V128] \to [\V128]`              :ref:`validation <validation <valid-vbinop>>`                :ref:`execution <execution <exec-vbinop>>`, :ref:`operator <operator <op-imax_u>>`      
 :math:`\I64X2.\VNEG`                         :math:`\hex{FD}~~193`  :math:`[\V128] \to [\V128]`                    :ref:`validation <validation <valid-vunop>>`                 :ref:`execution <execution <exec-vunop>>`, :ref:`operator <operator <op-ineg>>`         
+:math:`\I64x2.\BITMASK`                      :math:`\hex{FD}~~196`  :math:`[\V128] \to [\I32]`                     :ref:`validation <validation <valid-simd-bitmask>>`          :ref:`execution <execution <exec-simd-bitmask>>`                                        
 :math:`\I64X2.\VSHL`                         :math:`\hex{FD}~~203`  :math:`[\V128~\I32] \to [\V128]`               :ref:`validation <validation <valid-vshiftop>>`              :ref:`execution <execution <exec-vshiftop>>`, :ref:`operator <operator <op-ishl>>`      
 :math:`\I64X2.\VSHR\K{\_s}`                  :math:`\hex{FD}~~204`  :math:`[\V128~\I32] \to [\V128]`               :ref:`validation <validation <valid-vshiftop>>`              :ref:`execution <execution <exec-vshiftop>>`, :ref:`operator <operator <op-ishr_s>>`    
 :math:`\I64X2.\VSHR\K{\_u}`                  :math:`\hex{FD}~~205`  :math:`[\V128~\I32] \to [\V128]`               :ref:`validation <validation <valid-vshiftop>>`              :ref:`execution <execution <exec-vshiftop>>`, :ref:`operator <operator <op-ishr_u>>`    

diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst
@@ -667,6 +667,7 @@ All other SIMD instructions are plain opcodes without any immediates.
    \begin{array}{llclll}
    \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
      \hex{FD}~~193{:}\Bu32 &\Rightarrow& \I64X2.\VNEG \\ &&|&
+     \hex{FD}~~196{:}\Bu32 &\Rightarrow& \I64x2.\BITMASK \\ &&|&
      \hex{FD}~~203{:}\Bu32 &\Rightarrow& \I64X2.\VSHL \\ &&|&
      \hex{FD}~~204{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_s} \\ &&|&
      \hex{FD}~~205{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_u} \\ &&|&

diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst
@@ -232,7 +232,8 @@ SIMD instructions provide basic operations over :ref:`values <syntax-value>` of
      \K{i32x4.}\vitestop \\&&|&
      \K{i8x16.}\BITMASK ~|~
      \K{i16x8.}\BITMASK ~|~
-     \K{i32x4.}\BITMASK \\&&|&
+     \K{i32x4.}\BITMASK ~|~
+     \K{i64x2.}\BITMASK \\&&|&
      \K{i8x16.}\NARROW\K{\_i16x8\_}\sx ~|~
      \K{i16x8.}\NARROW\K{\_i32x4\_}\sx \\&&|&
      \K{i16x8.}\WIDEN\K{\_low}\K{\_i8x16\_}\sx ~|~

diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst
@@ -701,6 +701,7 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
    \begin{array}{llclll}
    \phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
      \text{i64x2.neg} &\Rightarrow& \I64X2.\VNEG\\ &&|&
+     \text{i64x2.bitmask} &\Rightarrow& \I64x2.\BITMASK\\ &&|&
      \text{i64x2.shl} &\Rightarrow& \I64X2.\VSHL\\ &&|&
      \text{i64x2.shr\_s} &\Rightarrow& \I64X2.\VSHR\K{\_s}\\ &&|&
      \text{i64x2.shr\_u} &\Rightarrow& \I64X2.\VSHR\K{\_u}\\ &&|&