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This however results in significant increase of simulation time (increasing with the amount of tcl IPs) on start of elaboration with warnings for each of the IPs:
# ELBREAD: Warning: Entity "xil_defaultlib.mycomponent" has been compiled after architecture "work.myfile(rtl)" that instantiates and binds this entity at simulation initialization. Recompile the source files in the correct order to perform the binding operation during compilation and simultaneously reduce the time required to initialize the simulation.
Note: Same warning does not show up for modelsim.
What would be the actual good way of solving this issue?
The text was updated successfully, but these errors were encountered:
Using
tsfpga
assume that I have 1 VHDL filemyfile.vhd
and 1 IP TCL file withmycomponent
.xil_defaultlib
libraryDuring the simulation now, In Riviera-PRO, simulator does not bind the generated IP properly to the component:
Solution discussion:
This seems to be easily fixed by updating
vunit/sim_if/rivierapro.py
->_create_load_function
by adding:which is added in modelsim also.
This however results in significant increase of simulation time (increasing with the amount of tcl IPs) on start of elaboration with warnings for each of the IPs:
Note: Same warning does not show up for modelsim.
What would be the actual good way of solving this issue?
The text was updated successfully, but these errors were encountered: