Merge remote-tracking branch 'origin/q' into auto-kernel

* origin/q:
  Revert "Remove Per File Key based hardware crypto framework"
  Revert "Integrate the new file encryption framework"
  Revert "Revert "Reverting crypto patches""
  Revert "Variant ops for UFS crypto and new crypto lib"
  Revert "mmc: host: Use request queue pointer for mmc crypto"
  Revert "mmc: cqhci: eMMC JEDEC v5.2 crypto spec addition"
  Revert "mmc: cqhci: Add eMMC crypto APIs"
  Revert "mmc: cqhci: Add inline crypto support to cqhci"
  Revert "mmc: host: Add variant ops for cqhci crypto"
  Revert "mmc: host: Fix the offset for ICE address"
  Revert "fscrypt: support legacy inline crypto mode"
  Revert "dm: Support legacy on disk format in dm-default-key"
  Revert "defconfig: Enable new file encryption flags"
  Revert "ARM: dts: Make crypto address part of host controller node"
  ARM: dts: msm: Changing the pet timeout as per granularity limit
  msm: ipa3: fix the unmap logic
  msm: ipa3: add support on detour lan2lan traffic to sw
  ARM: dts: sa2150p: enable rgmii level shifter on nand vt som
  sdm429w: add bg-rsg driver changes
  defconfig: Disable wlan vendors to optimize memory
  ARM: dts: Make crypto address part of host controller node
  defconfig: Enable new file encryption flags
  dm: Support legacy on disk format in dm-default-key
  fscrypt: support legacy inline crypto mode
  mmc: host: Fix the offset for ICE address
  mmc: host: Add variant ops for cqhci crypto
  mmc: cqhci: Add inline crypto support to cqhci
  mmc: cqhci: Add eMMC crypto APIs
  mmc: cqhci: eMMC JEDEC v5.2 crypto spec addition
  mmc: host: Use request queue pointer for mmc crypto
  Variant ops for UFS crypto and new crypto lib
  Revert "Reverting crypto patches"
  Integrate the new file encryption framework
  Remove Per File Key based hardware crypto framework
  ARM: dts: msm: Disable cti apps node for sa8155
  usb: f_gsi: Implement remote wakeup feature for gsi for bus suspend
  msm: ais: change the buffer SOF timestamp match
  lkdtm: Correct the size value for WRITE_KERN
  msm: kgsl: Always boot GMU with default CM3 config
  msm: kgsl: Add handler for GPC interrupt on A6xx GPU
  msm: ipa3: add eth ep_pair info
  msm: ipa3: add v2x ethernet pipes
  ARM: dts: msm: Add WLAN PD auxilary minidump ID for sdmmagpie
  ARM: dts: msm: Add WLAN PD auxilary minidump ID for MSS on SM6150
  RM: dts: msm: add support for gpio based jack detection on qcs610

Documentation/devicetree/bindings/soc/qcom/bg_rsb.txt

@@ -0,0 +1,19 @@
+Qualcomm technologies, Inc. bg-rsb
+
+BG-RSB : bg-rsb is used to communicate with Blackghost over
+Glink to configure the RSB events. bg-rsb enable/disable
+LDO11 and LDO15 before making any communication to BG
+regarding RSB. It also provides an input device, which is
+used to send the RSB/Button events to input framework.
+
+Required properties:
+- compatible : should be "qcom,bg-rsb"
+- vdd-ldo1-supply : for powering main supply
+- vdd-ldo2-supply : for powering sensor
+
+Example:
+	qcom,bg-rsb {
+		compatible = "qcom,bg-rsb";
+		vdd-ldo1-supply = <&pm660_l11>;
+		vdd-ldo2-supply = <&pm660_l15>;
+	};

arch/arm/configs/vendor/sdm429-bg-perf_defconfig

@@ -294,7 +294,21 @@ CONFIG_PPP_ASYNC=y
 CONFIG_PPP_SYNC_TTY=y
 CONFIG_USB_RTL8152=y
 CONFIG_USB_USBNET=y
-CONFIG_WIL6210=m
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
 CONFIG_WCNSS_MEM_PRE_ALLOC=y
 CONFIG_CLD_LL_CORE=y
 CONFIG_INPUT_EVDEV=y

arch/arm/configs/vendor/sdm429-bg_defconfig

@@ -301,6 +301,21 @@ CONFIG_PPP_ASYNC=y
 CONFIG_PPP_SYNC_TTY=y
 CONFIG_USB_RTL8152=y
 CONFIG_USB_USBNET=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
 CONFIG_WCNSS_MEM_PRE_ALLOC=y
 CONFIG_CLD_LL_CORE=y
 CONFIG_INPUT_EVDEV=y

arch/arm64/boot/dts/qcom/qcs610-ipc.dtsi

@@ -67,6 +67,13 @@
 	qcom,wsa-max-devs = <1>;
 	qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>;
 	qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft";
+	qcom,linein-det-swh = <1>;
+	qcom,lineout-det-swh = <1>;
+	qcom,linein-det-gpio = <&tlmm 1 0>;
+	qcom,lineout-det-gpio = <&tlmm 60 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&jack_det_linein_default
+		     &jack_det_lineout_default>;
 };
 
 &pm6150_charger {

arch/arm64/boot/dts/qcom/sa2145p-ccard-nand-dc.dts

@@ -81,3 +81,33 @@
 		rx-dll-bypass;
 	};
 };
+
+&tlmm {
+	/delete-node/ mdss_hdmi_ddc_active;
+	/delete-node/ mdss_hdmi_ddc_suspend;
+	rgmii_level_shifter: rgmii_level_shifter {
+		mux {
+			pins = "gpio16";
+			function = "gpio";
+		};
+		config {
+			pins = "gpio16";
+			drive-strength = <2>;
+			bias-pull-down;
+			output-low;
+		};
+	};
+};
+
+&ethqos_hw {
+	pinctrl-names = "dev-emac-mdc", "dev-emac-mdio",
+		"dev-emac-rgmii_txd0_state", "dev-emac-rgmii_txd1_state",
+		"dev-emac-rgmii_txd2_state", "dev-emac-rgmii_txd3_state",
+		"dev-emac-rgmii_txc_state",  "dev-emac-rgmii_tx_ctl_state",
+		"dev-emac-rgmii_rxd0_state", "dev-emac-rgmii_rxd1_state",
+		"dev-emac-rgmii_rxd2_state", "dev-emac-rgmii_rxd3_state",
+		"dev-emac-rgmii_rxc_state", "dev-emac-rgmii_rx_ctl_state",
+		"dev-emac-phy_intr", "dev-emac-phy_reset_state",
+		"dev-emac-rgmii_lvl_shift_state";
+	pinctrl-16 = <&rgmii_level_shifter>;
+};

arch/arm64/boot/dts/qcom/sa2150p-ccard-nand-dc.dts

@@ -155,3 +155,33 @@
 		rx-dll-bypass;
 	};
 };
+
+&tlmm {
+	/delete-node/ mdss_hdmi_ddc_active;
+	/delete-node/ mdss_hdmi_ddc_suspend;
+	rgmii_level_shifter: rgmii_level_shifter {
+		mux {
+			pins = "gpio16";
+			function = "gpio";
+		};
+		config {
+			pins = "gpio16";
+			drive-strength = <2>;
+			bias-pull-down;
+			output-low;
+		};
+	};
+};
+
+&ethqos_hw {
+	pinctrl-names = "dev-emac-mdc", "dev-emac-mdio",
+		"dev-emac-rgmii_txd0_state", "dev-emac-rgmii_txd1_state",
+		"dev-emac-rgmii_txd2_state", "dev-emac-rgmii_txd3_state",
+		"dev-emac-rgmii_txc_state",  "dev-emac-rgmii_tx_ctl_state",
+		"dev-emac-rgmii_rxd0_state", "dev-emac-rgmii_rxd1_state",
+		"dev-emac-rgmii_rxd2_state", "dev-emac-rgmii_rxd3_state",
+		"dev-emac-rgmii_rxc_state", "dev-emac-rgmii_rx_ctl_state",
+		"dev-emac-phy_intr", "dev-emac-phy_reset_state",
+		"dev-emac-rgmii_lvl_shift_state";
+	pinctrl-16 = <&rgmii_level_shifter>;
+};

arch/arm64/boot/dts/qcom/sa8155.dtsi

@@ -786,6 +786,38 @@
 	status="disabled";
 };
 
+&cti_cpu0 {
+	status = "disabled";
+};
+
+&cti_cpu1 {
+	status = "disabled";
+};
+
+&cti_cpu2 {
+	status = "disabled";
+};
+
+&cti_cpu3 {
+	status = "disabled";
+};
+
+&cti_cpu4 {
+	status = "disabled";
+};
+
+&cti_cpu5 {
+	status = "disabled";
+};
+
+&cti_cpu6 {
+	status = "disabled";
+};
+
+&cti_cpu7 {
+	status = "disabled";
+};
+
 #include "sa8155-audio.dtsi"
 #include "sa8155-camera.dtsi"
 #include "sa8155-camera-sensor.dtsi"

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

@@ -2631,6 +2631,7 @@
 		qcom,smem-id = <421>;
 		qcom,signal-aop;
 		qcom,minidump-id = <3>;
+		qcom,aux-minidump-ids = <4>;
 		qcom,complete-ramdump;
 
 		qcom,msm-bus,name = "pil-modem";

arch/arm64/boot/dts/qcom/sdxprairie.dtsi

@@ -264,7 +264,7 @@
 		reg-names = "wdt-base";
 		interrupts = <1 3 0>, <1 2 0>;
 		qcom,bark-time = <11000>;
-		qcom,pet-time = <10000>;
+		qcom,pet-time = <9360>;
 		qcom,wakeup-enable;
 	};
 

arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi

@@ -1146,6 +1146,35 @@
 			};
 		};
 
+
+		gpio_jack_det_line_in {
+			jack_det_linein_default: jack_det_linein_default {
+				mux {
+					pins = "gpio1";
+					function = "gpio";
+				};
+				config {
+					pins = "gpio1";
+					bias-pull-up; /* pull up */
+					input-enable;
+				};
+			};
+		};
+
+		gpio_jack_det_line_out {
+			jack_det_lineout_default: jack_det_lineout_default {
+				mux {
+					pins = "gpio60";
+					function = "gpio";
+				};
+				config {
+					pins = "gpio60";
+					bias-pull-up; /* pull up */
+					input-enable;
+				};
+			};
+		};
+
 		ter_i2s_sck_ws {
 			ter_i2s_sck_sleep: ter_i2s_sck_sleep {
 				mux {

arch/arm64/boot/dts/qcom/sm6150.dtsi

@@ -2428,6 +2428,7 @@
 		qcom,smem-id = <421>;
 		qcom,signal-aop;
 		qcom,minidump-id = <3>;
+		qcom,aux-minidump-ids = <4>;
 		qcom,complete-ramdump;
 
 		/* Inputs from mss */

drivers/gpu/msm/adreno_a5xx.c

@@ -3315,11 +3315,11 @@ static void a5xx_gpmu_int_callback(struct adreno_device *adreno_dev, int bit)
 }
 
 /*
- * a5x_gpc_err_int_callback() - Isr for GPC error interrupts
+ * a5xx_gpc_err_int_callback() - Isr for GPC error interrupts
  * @adreno_dev: Pointer to device
  * @bit: Interrupt bit
  */
-void a5x_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
+static void a5xx_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
 {
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 
@@ -3329,7 +3329,7 @@ void a5x_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
 	 * with help of register dump.
 	 */
 
-	KGSL_DRV_CRIT(device, "RBBM: GPC error\n");
+	KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: GPC error\n");
 	adreno_irqctrl(adreno_dev, 0);
 
 	/* Trigger a fault in the dispatcher - this will effect a restart */
@@ -3367,7 +3367,7 @@ static struct adreno_irq_funcs a5xx_irq_funcs[32] = {
 	ADRENO_IRQ_CALLBACK(a5xx_err_callback),
 	/* 6 - RBBM_ATB_ASYNC_OVERFLOW */
 	ADRENO_IRQ_CALLBACK(a5xx_err_callback),
-	ADRENO_IRQ_CALLBACK(a5x_gpc_err_int_callback), /* 7 - GPC_ERR */
+	ADRENO_IRQ_CALLBACK(a5xx_gpc_err_int_callback), /* 7 - GPC_ERR */
 	ADRENO_IRQ_CALLBACK(a5xx_preempt_callback),/* 8 - CP_SW */
 	ADRENO_IRQ_CALLBACK(a5xx_cp_hw_err_callback), /* 9 - CP_HW_ERROR */
 	/* 10 - CP_CCU_FLUSH_DEPTH_TS */

drivers/gpu/msm/adreno_a6xx.c

@@ -1760,6 +1760,29 @@ static void a6xx_cp_callback(struct adreno_device *adreno_dev, int bit)
 	adreno_dispatcher_schedule(device);
 }
 
+/*
+ * a6xx_gpc_err_int_callback() - Isr for GPC error interrupts
+ * @adreno_dev: Pointer to device
+ * @bit: Interrupt bit
+ */
+static void a6xx_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)
+{
+	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+
+	/*
+	 * GPC error is typically the result of mistake SW programming.
+	 * Force GPU fault for this interrupt so that we can debug it
+	 * with help of register dump.
+	 */
+
+	KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: GPC error\n");
+	adreno_irqctrl(adreno_dev, 0);
+
+	/* Trigger a fault in the dispatcher - this will effect a restart */
+	adreno_set_gpu_fault(adreno_dev, ADRENO_SOFT_FAULT);
+	adreno_dispatcher_schedule(device);
+}
+
 #define A6XX_INT_MASK \
 	((1 << A6XX_INT_CP_AHB_ERROR) |			\
 	 (1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) |	\
@@ -1785,7 +1808,7 @@ static struct adreno_irq_funcs a6xx_irq_funcs[32] = {
 	ADRENO_IRQ_CALLBACK(NULL), /* 5 - UNUSED */
 	/* 6 - RBBM_ATB_ASYNC_OVERFLOW */
 	ADRENO_IRQ_CALLBACK(a6xx_err_callback),
-	ADRENO_IRQ_CALLBACK(NULL), /* 7 - GPC_ERR */
+	ADRENO_IRQ_CALLBACK(a6xx_gpc_err_int_callback), /* 7 - GPC_ERR */
 	ADRENO_IRQ_CALLBACK(a6xx_preemption_callback),/* 8 - CP_SW */
 	ADRENO_IRQ_CALLBACK(a6xx_cp_hw_err_callback), /* 9 - CP_HW_ERROR */
 	ADRENO_IRQ_CALLBACK(NULL),  /* 10 - CP_CCU_FLUSH_DEPTH_TS */

drivers/gpu/msm/adreno_a6xx_gmu.c

@@ -1,4 +1,4 @@
-/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -350,6 +350,8 @@ static int a6xx_gmu_start(struct kgsl_device *device)
 
 	/* Bring GMU out of reset */
 	gmu_core_regwrite(device, A6XX_GMU_CM3_SYSRESET, 0);
+	/* Make sure the request completes before continuing */
+	wmb();
 	if (timed_poll_check(device,
 			A6XX_GMU_CM3_FW_INIT_RESULT,
 			0xBABEFACE,
@@ -1047,6 +1049,13 @@ static int a6xx_gmu_fw_start(struct kgsl_device *device,
 	gmu_core_regwrite(device, A6XX_GMU_AHB_FENCE_RANGE_0,
 			GMU_FENCE_RANGE_MASK);
 
+	/*
+	 * Make sure that CM3 state is at reset value. Snapshot is changing
+	 * NMI bit and if we boot up GMU with NMI bit set.GMU will boot straight
+	 * in to NMI handler without executing __main code
+	 */
+	gmu_core_regwrite(device, A6XX_GMU_CM3_CFG, 0x4052);
+
 	/* Pass chipid to GMU FW, must happen before starting GMU */
 
 	/* Keep Core and Major bitfields unchanged */

drivers/gpu/msm/kgsl_gmu.c

@@ -964,6 +964,8 @@ static int gmu_rpmh_init(struct kgsl_device *device,
 
 static void send_nmi_to_gmu(struct adreno_device *adreno_dev)
 {
+	u32 val;
+
 	/* Mask so there's no interrupt caused by NMI */
 	adreno_write_gmureg(adreno_dev,
 			ADRENO_REG_GMU_GMU2HOST_INTR_MASK, 0xFFFFFFFF);
@@ -972,9 +974,10 @@ static void send_nmi_to_gmu(struct adreno_device *adreno_dev)
 	wmb();
 	adreno_write_gmureg(adreno_dev,
 		ADRENO_REG_GMU_NMI_CONTROL_STATUS, 0);
-	adreno_write_gmureg(adreno_dev,
-		ADRENO_REG_GMU_CM3_CFG,
-		(1 << GMU_CM3_CFG_NONMASKINTR_SHIFT));
+
+	adreno_read_gmureg(adreno_dev, ADRENO_REG_GMU_CM3_CFG, &val);
+	val |= 1 << GMU_CM3_CFG_NONMASKINTR_SHIFT;
+	adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_CM3_CFG, val);
 
 	/* Make sure the NMI is invoked before we proceed*/
 	wmb();