Merge pull request eclipse-omr#7357 from 0xdaryl/tlhprefetch

Disable TLH prefetching by default post-Skylake processors
ThanHenderson · Jun 5, 2024 · 384dcb8 · 384dcb8
2 parents 753ebae + 773a2df
commit 384dcb8
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Showing 3 changed files with 2 additions and 38 deletions.
diff --git a/compiler/x/codegen/OMRCodeGenerator.cpp b/compiler/x/codegen/OMRCodeGenerator.cpp
@@ -323,15 +323,7 @@ OMR::X86::CodeGenerator::initializeX86(TR::Compilation *comp)
       self()->setXMMDoubleLoadOpCode(TR::InstOpCode::MOVSDRegMem);
       }
 
-   self()->setTargetSupportsSoftwarePrefetches();
-
-   // Enable software prefetch of the TLH and configure the TLH prefetching
-   // geometry.
-   //
-   TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_CORE2) == comp->cg()->getX86ProcessorInfo().isIntelCore2(), "isIntelCore2() failed\n");
-   TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_NEHALEM) == comp->cg()->getX86ProcessorInfo().isIntelNehalem(), "isIntelNehalem() failed\n");
-   if (((!comp->getOption(TR_DisableTLHPrefetch) && (comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_CORE2) || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_NEHALEM))) ||
-       (comp->getOption(TR_TLHPrefetch) && self()->targetSupportsSoftwarePrefetches())))
+   if (comp->getOption(TR_TLHPrefetch))
       {
       self()->setEnableTLHPrefetching();
       }

diff --git a/compiler/x/codegen/OMRCodeGenerator.hpp b/compiler/x/codegen/OMRCodeGenerator.hpp
@@ -800,7 +800,7 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
       EnableTLHPrefetching                     = 0x00000800, ///< enable software prefetches on TLH allocates
       // Available                             = 0x00001000,
       // Available                             = 0x00002000,
-      TargetSupportsSoftwarePrefetches         = 0x00004000, ///< target processor and OS both support software prefetch instructions
+      // Available                             = 0x00004000,
       MethodEnterExitTracingEnabled            = 0x00008000, ///< trace method enter/exits
       // Available                             = 0x00010000,
       PushPreservedRegisters                   = 0x00020000  ///< we've chosen to save/restore preserved regs using push/pop instructions instead of movs
@@ -848,12 +848,6 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
       }
    void setEnableRegisterAssociations() {_flags.set(EnableRegisterAssociations);}
 
-   bool targetSupportsSoftwarePrefetches()
-      {
-      return _flags.testAny(TargetSupportsSoftwarePrefetches);
-      }
-   void setTargetSupportsSoftwarePrefetches() {_flags.set(TargetSupportsSoftwarePrefetches);}
-
    bool enableTLHPrefetching()
       {
       return _flags.testAny(EnableTLHPrefetching);

diff --git a/include_core/omrport.h b/include_core/omrport.h
@@ -1479,28 +1479,6 @@ typedef enum OMRProcessorArchitecture {
 	OMR_PROCESSOR_X86_AMD_FAMILY15H,
 	OMR_PROCESSOR_X86_AMD_LAST = OMR_PROCESSOR_X86_AMD_FAMILY15H,
 
-	/**
-	 * Keep the original macro definitions until all known downstream projects
-	 * complete the switch to the new names
-	 */
-	// <ORIGINAL MACROS>
-	OMR_PROCESSOR_X86_INTELPENTIUM = OMR_PROCESSOR_X86_INTEL_PENTIUM,
-	OMR_PROCESSOR_X86_INTELP6 = OMR_PROCESSOR_X86_INTEL_P6,
-	OMR_PROCESSOR_X86_INTELPENTIUM4 = OMR_PROCESSOR_X86_INTEL_PENTIUM4,
-	OMR_PROCESSOR_X86_INTELCORE2 = OMR_PROCESSOR_X86_INTEL_CORE2,
-	OMR_PROCESSOR_X86_INTELTULSA = OMR_PROCESSOR_X86_INTEL_TULSA,
-	OMR_PROCESSOR_X86_INTELNEHALEM = OMR_PROCESSOR_X86_INTEL_NEHALEM,
-	OMR_PROCESSOR_X86_INTELWESTMERE = OMR_PROCESSOR_X86_INTEL_WESTMERE,
-	OMR_PROCESSOR_X86_INTELSANDYBRIDGE = OMR_PROCESSOR_X86_INTEL_SANDYBRIDGE,
-	OMR_PROCESSOR_X86_INTELIVYBRIDGE = OMR_PROCESSOR_X86_INTEL_IVYBRIDGE,
-	OMR_PROCESSOR_X86_INTELHASWELL = OMR_PROCESSOR_X86_INTEL_HASWELL,
-	OMR_PROCESSOR_X86_INTELBROADWELL = OMR_PROCESSOR_X86_INTEL_BROADWELL,
-	OMR_PROCESSOR_X86_INTELSKYLAKE = OMR_PROCESSOR_X86_INTEL_SKYLAKE,
-	OMR_PROCESSOR_X86_AMDATHLONDURON = OMR_PROCESSOR_X86_AMD_ATHLONDURON,
-	OMR_PROCESSOR_X86_AMDOPTERON = OMR_PROCESSOR_X86_AMD_OPTERON,
-	OMR_PROCESSOR_X86_AMDFAMILY15H = OMR_PROCESSOR_X86_AMD_FAMILY15H,
-	// </ORIGINAL MACROS>
-
 	OMR_PROCESSOR_X86_LAST = OMR_PROCESSOR_X86_AMD_FAMILY15H,
 
 	OMR_PROCESSOR_RISCV32_UNKNOWN,