fix: linter vivado with SV

TerosTechnology · Jul 13, 2023 · 86917f2 · 86917f2
1 parent 0572e58
commit 86917f2
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Showing 7 changed files with 21 additions and 15 deletions.
diff --git a/packages/colibri/src/config/config_web.ts b/packages/colibri/src/config/config_web.ts
@@ -1166,7 +1166,7 @@ export const WEB_CONFIG = `
           
           
             <div class="mb-3">
-              <label for="linter-modelsim-verilog_arguments" class="form-label">Verilog linter arguments.</label>
+              <label for="linter-modelsim-verilog_arguments" class="form-label">Verilog/SV linter arguments.</label>
               <input class="form-control" id="linter-modelsim-verilog_arguments" rows="3"  value=""></input>
             </div>
           
@@ -1249,7 +1249,7 @@ export const WEB_CONFIG = `
           
           
             <div class="mb-3">
-              <label for="linter-vivado-verilog_arguments" class="form-label">Verilog linter arguments.</label>
+              <label for="linter-vivado-verilog_arguments" class="form-label">Verilog/SV linter arguments.</label>
               <input class="form-control" id="linter-vivado-verilog_arguments" rows="3"  value=""></input>
             </div>
           

diff --git a/packages/colibri/src/config/helpers/configs/linter/modelsim.yml b/packages/colibri/src/config/helpers/configs/linter/modelsim.yml
@@ -4,6 +4,6 @@ vhdl_arguments:
   value: ""
 
 verilog_arguments:
-  description: "Verilog linter arguments."
+  description: "Verilog/SV linter arguments."
   type: string
   value: ""
diff --git a/packages/colibri/src/config/helpers/configs/linter/vivado.yml b/packages/colibri/src/config/helpers/configs/linter/vivado.yml
@@ -4,6 +4,6 @@ vhdl_arguments:
   value: ""
 
 verilog_arguments:
-  description: "Verilog linter arguments."
+  description: "Verilog/SV linter arguments."
   type: string
   value: ""
diff --git a/packages/colibri/src/config/web_config.html b/packages/colibri/src/config/web_config.html
@@ -1146,7 +1146,7 @@ <h6 class="card-subtitle mb-2 text-muted"></h6>
 
 
             <div class="mb-3">
-              <label for="linter-modelsim-verilog_arguments" class="form-label">Verilog linter arguments.</label>
+              <label for="linter-modelsim-verilog_arguments" class="form-label">Verilog/SV linter arguments.</label>
               <input class="form-control" id="linter-modelsim-verilog_arguments" rows="3"  value=""></input>
             </div>
 
@@ -1229,7 +1229,7 @@ <h6 class="card-subtitle mb-2 text-muted"></h6>
 
 
             <div class="mb-3">
-              <label for="linter-vivado-verilog_arguments" class="form-label">Verilog linter arguments.</label>
+              <label for="linter-vivado-verilog_arguments" class="form-label">Verilog/SV linter arguments.</label>
               <input class="form-control" id="linter-vivado-verilog_arguments" rows="3"  value=""></input>
             </div>
 

diff --git a/packages/colibri/src/linter/vivado.ts b/packages/colibri/src/linter/vivado.ts
@@ -43,7 +43,7 @@ export class Vivado extends Base_linter {
             binary = "xvhdl";
         }
         else if (file_lang === HDL_LANG.SYSTEMVERILOG) {
-            binary = "xvlog";
+            binary = `xvlog ${this.sv_options}`;
         }
         else {
             binary = "xvlog";

diff --git a/packages/teroshdl/auto_package/templates/info.nj b/packages/teroshdl/auto_package/templates/info.nj
@@ -2,7 +2,7 @@
 "displayName": "TerosHDL",
 "publisher": "teros-technology",
 "description": "Powerful IDE for ASIC/FPGA: state machine viewer, linter, documentation, snippets... and more! ",
-"version": "5.0.2",
+"version": "5.0.3",
 "engines": {
     "vscode": "^1.74.0"
 },

diff --git a/packages/teroshdl/src/features/linter.ts b/packages/teroshdl/src/features/linter.ts
@@ -73,7 +73,7 @@ class Linter {
         }
     }
 
-    private get_options(): teroshdl2.linter.common.l_options {
+    private get_options(lang: teroshdl2.common.general.HDL_LANG): teroshdl2.linter.common.l_options {
         let path = "";
         let argument = "";
         const linter_name = this.get_linter_name();
@@ -82,27 +82,31 @@ class Linter {
             path = this.get_config().tools.ghdl.installation_path;
             argument = this.get_config().linter.ghdl.arguments;
         }
-        else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_vhdl.modelsim){
+        else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_vhdl.modelsim &&
+                lang === teroshdl2.common.general.HDL_LANG.VHDL){
             path = this.get_config().tools.modelsim.installation_path;
             argument = this.get_config().linter.modelsim.vhdl_arguments;
         }
-        else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_vhdl.vivado){
+        else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_vhdl.vivado &&
+                lang === teroshdl2.common.general.HDL_LANG.VHDL){
             path = this.get_config().tools.vivado.installation_path;
             argument = this.get_config().linter.vivado.vhdl_arguments;
         }
         else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_verilog.icarus){
             path = this.get_config().tools.icarus.installation_path;
             argument = this.get_config().linter.icarus.arguments;
         }
-        else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_verilog.modelsim){
+        else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_verilog.modelsim &&
+                lang !== teroshdl2.common.general.HDL_LANG.VHDL){
             path = this.get_config().tools.modelsim.installation_path;
             argument = this.get_config().linter.vivado.verilog_arguments;
         }
         else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_verilog.verilator){
             path = this.get_config().tools.verilator.installation_path;
             argument = this.get_config().linter.verilator.arguments;
         }
-        else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_verilog.vivado){
+        else if (linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_verilog.vivado &&
+                lang !== teroshdl2.common.general.HDL_LANG.VHDL){
             path = this.get_config().tools.vivado.installation_path;
             argument = this.get_config().linter.vivado.verilog_arguments;
         }
@@ -165,7 +169,7 @@ class Linter {
 
         console.log(`[terosHDL] Linting ${current_path}`);
 
-        let errors = await this.linter.lint_from_file(linter_name, current_path, this.get_options());
+        let errors = await this.linter.lint_from_file(linter_name, current_path, this.get_options(lang),);
 
         let diagnostics: vscode.Diagnostic[] = [];
         for (var i = 0; i < errors.length; ++i) {
@@ -193,7 +197,9 @@ class Linter {
         let current_path = uri.fsPath;
         const linter_name = this.get_linter_name();
 
-        let errors = await this.linter.lint_from_file(linter_name, current_path, this.get_options());
+        const lang = teroshdl2.utils.hdl.get_lang_from_path(current_path);
+
+        let errors = await this.linter.lint_from_file(linter_name, current_path, this.get_options(lang));
         let diagnostics: vscode.Diagnostic[] = [];
         if (empty === true 
             || linter_name === teroshdl2.config.config_declaration.e_linter_general_linter_vhdl.none