designing a rtl verilog code for 24 hours digital clock. the output is represent using 6- seven segment . 6- seven segment used for sec_l,sem_m,min_l, min_m,hr_l,hr_m. the design have two inputs clk and rst and 6 outputs which represents using 6-seven segment . top module design using counter and bcd to seven segment block design instantiation.
BLOCK DESGIN-
- TOP MODULE
- COUNTER
3)BCD_SEVEN_SEGMENT
WAVEFORM
