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[RISCV] Handle f16/bf16 extract_vector_elt when scalar type is legal (l…
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…lvm#110144)

When the scalar type is illegal, it gets softened during type
legalization and gets lowered as an integer.

However with zfhmin/zfbfmin the type is now legal and it passes through
type legalization where it crashes because we didn't have any custom
lowering or patterns for it.

This handles said case via the existing custom lowering to a vslidedown
and vfmv.f.s.
It also handles the case where we only have zvfhmin/zvfbfmin and don't
have vfmv.f.s, in which case we need to extract it to a GPR and then use
fmv.h.x.

Fixes llvm#110126
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lukel97 authored and Sterling-Augustine committed Sep 27, 2024
1 parent 8441270 commit 0a62d9f
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15 changes: 13 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1082,8 +1082,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
VT, Custom);
MVT EltVT = VT.getVectorElementType();
if (isTypeLegal(EltVT))
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT}, VT,
Custom);
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT,
ISD::EXTRACT_VECTOR_ELT},
VT, Custom);
else
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT},
EltVT, Custom);
Expand Down Expand Up @@ -8990,6 +8991,16 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec, Idx);
}

if ((EltVT == MVT::f16 && !Subtarget.hasVInstructionsF16()) ||
EltVT == MVT::bf16) {
// If we don't have vfmv.f.s for f16/bf16, extract to a gpr then use fmv.h.x
MVT IntVT = VecVT.changeTypeToInteger();
SDValue IntVec = DAG.getBitcast(IntVT, Vec);
SDValue IntExtract =
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, XLenVT, IntVec, Idx);
return DAG.getNode(RISCVISD::FMV_H_X, DL, EltVT, IntExtract);
}

// If this is a fixed vector, we need to convert it to a scalable vector.
MVT ContainerVT = VecVT;
if (VecVT.isFixedLengthVector()) {
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