[WIP] extend full sn32f2xx family support

os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h

@@ -1,29 +1,6 @@
 #ifndef __SN32F200_DEF_H
 #define __SN32F200_DEF_H
 
-/*_____ I N C L U D E S ____________________________________________________*/
-
-/*_____ D E F I N I T I O N S ______________________________________________*/
-
-//Ture or False
-// #define TRUE		0x1
-// #define FALSE		0x0
-
-//Enable or Disable
-#define ENABLE		0x1
-#define DISABLE		0x0
-
-//Error Status
-#define	OK			0x0
-#define	FAIL		0x1
-
-//Null
-// #define NULL		0
-
-//Interrupt Flag Parsing Method
-#define	POLLING_METHOD		0x0
-#define	INTERRUPT_METHOD	0x1
-
 //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 //SN32F230_PKG
 #define	SN32F239 		0
@@ -45,13 +22,29 @@
 #define	SN32F246B		2
 #define	SN32F2451B		3
 
+//SN32F240C_PKG
+#define	SN32F248C 		0
+#define	SN32F247C		1
+#define	SN32F246C		2
+#define	SN32F2451C		3
+
 //SN32F260_PKG
 #define	SN32F268 		0
 #define	SN32F267		1
 #define	SN32F265		2
 #define	SN32F2641		3
 #define	SN32F264		4
 #define	SN32F263		5
+
+//SN32F280_PKG
+#define	SN32F289 		0
+#define	SN32F288		1
+#define	SN32F287		2
+
+//SN32F290_PKG
+#define	SN32F299 		0
+#define	SN32F298		1
+#define	SN32F297		2
 //;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 /*_____ M A C R O S ________________________________________________________*/

os/common/ext/SONiX/SN32F2xx/SN32F2xx.h

@@ -20,11 +20,12 @@
    application 
   */
 
-#if !defined (SN32F240) && !defined (SN32F240B) && !defined (SN32F260) \
-    && !defined (SN32F280) && !defined (SN32F290)
+#if !defined (SN32F240) && !defined (SN32F240B) && !defined (SN32F240C) \
+    && !defined (SN32F260) && !defined (SN32F280) && !defined (SN32F290)
   /* #define SN32F230 */   /*!< SN32F239, SN32F238, SN32F237, SN32F236,and SN32F235 Devices */
   /* #define SN32F240 */   /*!< SN32F249, SN32F248, SN32F247, SN32F246 and SN32F245 Devices */
   /* #define SN32F240B */  /*!< SN32F248B, SN32F247B, SN32F246B and SN32F2451B Devices */
+  /* #define SN32F240C */  /*!< SN32F248C, SN32F247C, SN32F246C and SN32F2451C Devices */
   /* #define SN32F260 */   /*!< SN32F268, SN32F267, SN32F265, SN32F2641,
                                    SN32F264 and SN32F263 Devices */
   /* #define SN32F280 */   /*!< SN32F289, SN32F288 and SN32F287 Devices */
@@ -40,6 +41,8 @@
   #include "SN32F240.h"
 #elif defined(SN32F240B)
   #include "SN32F240B.h"
+#elif defined(SN32F240C)
+  #include "SN32F240C.h"
 #elif defined(SN32F260)
   #include "SN32F260.h"
 #elif defined(SN32F280)

os/common/ext/SONiX/SN32F2xx/system_SN32F240C.c

@@ -0,0 +1,257 @@
+/******************************************************************************
+ * @file     system_SN32F240C.c
+ * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Source File
+ *           for the SONIX SN32F240C Devices
+ * @version  V1.0.0
+ * @date     2021/09/02
+ *
+ * @note
+ * Copyright (C) 2020-2024 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include <system_SN32F2xx.h>
+#include <mcuconf.h>
+#include <sn32_sys1.h>
+
+
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+//		<o0.0..2>  SYSCLKSEL (SYS0_CLKCFG)
+//					<0=> IHRC
+//					<1=> ILRC
+//					<4=> PLL
+//
+//
+//<e1> PLL ENABLE
+//	<h> PLL Control Register (SYS0_PLLCTRL)
+//			<i> F_CLKOUT = F_VCO / P = (F_CLKIN * M) / P
+//			<i> 10 MHz <= F_CLKIN <= 25 MHz
+//			<i> 96 MHz <= (F_CLKIN * M) <= 144 MHz
+//		<o2> MSEL
+//					<0=> M = 4
+//					<1=> M = 6
+//					<2=> M = 8
+//					<3=> M = 10
+//					<4=> M = 12
+//		<o3> PSEL
+//					<0=> P = 2
+//					<1=> P = 4
+//	</h>
+//</e>
+//		<o4>  AHB Clock Prescaler Register  (SYS0_AHBCP)
+//					<0=> SYSCLK/1
+//					<1=> SYSCLK/2
+//					<2=> SYSCLK/4
+//					<3=> SYSCLK/8
+//					<4=> SYSCLK/16
+//					<5=> SYSCLK/32
+//					<6=> SYSCLK/64
+//					<7=> SYSCLK/128
+//		<o5>  SYSCLK prescaler Register  (SYS0_AHBCP)
+//					<0=> SYSCLK/1
+//					<1=> SYSCLK/1.5
+//		<o6>  CLKOUT selection
+//					<0=> Disable
+//					<1=> ILRC
+//					<4=> HCLK
+//					<5=> IHRC
+//					<7=> PLL
+//		<o7> CLKOUT Prescaler Register  (SYS1_APBCP1)
+//					<0=> CLKOUT selection/1
+//					<1=> CLKOUT selection/2
+//					<2=> CLKOUT selection/4
+//					<3=> CLKOUT selection/8
+//					<4=> CLKOUT selection/16
+//					<5=> CLKOUT selection/32
+//					<6=> CLKOUT selection/64
+//					<7=> CLKOUT selection/128
+*/
+
+#ifndef SYS0_CLKCFG_VAL
+#define SYS0_CLKCFG_VAL		4
+#endif
+#ifndef PLL_ENABLE
+#define PLL_ENABLE				1
+#endif
+#ifndef PLL_MSEL
+#define PLL_MSEL					2
+#endif
+#ifndef PLL_PSEL
+#define PLL_PSEL					0
+#endif
+#ifndef AHB_PRESCALAR
+#define AHB_PRESCALAR 		0x0
+#endif
+#ifndef AHB_1P5PRESCALAR
+#define AHB_1P5PRESCALAR 	0x0
+#endif
+#ifndef CLKOUT_SEL_VAL
+#define CLKOUT_SEL_VAL 		0x0
+#endif
+#ifndef CLKOUT_PRESCALAR
+#define CLKOUT_PRESCALAR 	0x0
+#endif
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+#ifndef IHRC
+#define	IHRC			0
+#endif
+#ifndef ILRC
+#define	ILRC			1
+#endif
+#ifndef PLL
+#define PLL				4
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __IHRC_FREQ			(12000000UL)
+#define __ILRC_FREQ			(32000UL)
+
+#define SYS0_PLLCTRL_VAL	(PLL_ENABLE<<15) | (PLL_PSEL<<5) |  PLL_MSEL
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock;	/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+	uint32_t AHB_prescaler = 0;
+
+	switch (SN_SYS0->CLKCFG_b.SYSCLKST)
+	{
+		case 0:		//IHRC
+			SystemCoreClock = __IHRC_FREQ;
+			break;
+		case 1:		//ILRC
+			SystemCoreClock = __ILRC_FREQ;
+			break;
+		case 4: 	//PLL
+			SystemCoreClock = __IHRC_FREQ * (PLL_MSEL+2) / (PLL_PSEL+1);
+			break;
+		default:
+			break;
+	}
+
+	switch (SN_SYS0->AHBCP_b.AHBPRE)
+	{
+		case 0:	AHB_prescaler = 1;	break;
+		case 1:	AHB_prescaler = 2;	break;
+		case 2:	AHB_prescaler = 4;	break;
+		case 3:	AHB_prescaler = 8;	break;
+		case 4:	AHB_prescaler = 16;	break;
+		case 5:	AHB_prescaler = 32;	break;
+		case 6:	AHB_prescaler = 64;	break;
+		case 7:	AHB_prescaler = 128;break;
+		default: break;	
+	}
+
+	SystemCoreClock /= AHB_prescaler;
+}
+/**
+ * Initialize the Flash controller
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Update the Flash power control.
+ */
+void FlashClockUpdate (void)
+{
+
+	//;;;;;;;;; Need for SN32F240C Begin	;;;;;;;;;
+	if (SystemCoreClock > 48000000)
+		SN_FLASH->LPCTRL = 0x5AFA0039;
+	else if (SystemCoreClock >= 24000000)
+		SN_FLASH->LPCTRL = 0x5AFA0029;
+	else  //Slow mode required for SystemCoreClock <= 24000000
+		SlowModeSwitch();
+	//;;;;;;;;; Need for SN32F240C End	;;;;;;;;;
+}
+
+/**
+ * Switch System to Slow Mode
+ * @param  none
+ * @return none
+ *
+ * @brief  Special init required for SystemCoreClock <= 24000000
+ */
+void SlowModeSwitch (void)
+{
+	SN_SYS0->CLKCFG_b.SYSCLKSEL = 0; //Switch to IHRC
+	SystemCoreClockUpdate();
+	SN_FLASH->LPCTRL = 0x5AFA0000;
+}
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+	#if SYS0_CLKCFG_VAL == IHRC			//IHRC
+	SN_SYS0->CLKCFG = 0x0;
+	while ((SN_SYS0->CLKCFG & 0x70) != 0x0);
+	#endif
+
+	#if SYS0_CLKCFG_VAL == ILRC			//ILRC
+	SN_SYS0->CLKCFG = 0x1;
+	while ((SN_SYS0->CLKCFG & 0x70) != 0x10);
+	#endif
+
+	#if (PLL_ENABLE == 1)
+	SN_FLASH->LPCTRL = 0x5AFA0039;
+	SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL;
+	while ((SN_SYS0->CSST & 0x40) != 0x40);
+	#if (SYS0_CLKCFG_VAL == PLL)		//PLL
+	SN_SYS0->CLKCFG = 0x4;
+	while ((SN_SYS0->CLKCFG & 0x70) != 0x40);
+	#endif
+	#endif
+
+	SN_SYS0->AHBCP = AHB_PRESCALAR;
+
+	#if (CLKOUT_SEL_VAL > 0)			//CLKOUT
+	SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL;
+	SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR;
+	#endif
+}