WiSeConnect 3 SDK release: v3.3.1-alpha1

SiliconLabs · Aug 7, 2024 · 664768c · 664768c
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commit 664768c
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Showing 294 changed files with 2,180 additions and 601 deletions.
diff --git a/components/device/silabs/si91x/mcu/core/chip/component/device_needs_ram_execution.slcc b/components/device/silabs/si91x/mcu/core/chip/component/device_needs_ram_execution.slcc
@@ -11,11 +11,11 @@ provides:
   - name: device_needs_ram_execution
 define:
   - name: SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION
+  - name: SLI_SI91X_MCU_ENABLE_PSRAM_SECTION_FEATURE
+    condition: [wiseconnect_toolchain_psram_linker]   
 template_contribution:
   - name: ram_execution
     value: true
   - name: device_ram_addr
     value: 1024
     priority: -2
-conflicts:
-  - name: text_segment_in_psram
diff --git a/components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c b/components/device/silabs/si91x/mcu/core/chip/src/startup_si91x.c
@@ -57,13 +57,16 @@ extern unsigned long _sidata;       /*!< Start address for the initialization
                                       values of the .data section.            */
 extern unsigned long _sdata;        /*!< Start address for the .data section     */
 extern unsigned long _edata;        /*!< End address for the .data section       */
-extern unsigned long _slpcode;      /*!< Start address for the initialization
-                                      values of the .sleep_psram_driver section.            */
-extern unsigned long _scode;        /*!< Start address for the .sleep_psram_driver section     */
-extern unsigned long _ecode;        /*!< End address for the .sleep_psram_driver section       */
 extern unsigned long __bss_start__; /*!< Start address for the .bss section     */
 extern unsigned long __bss_end__;   /*!< End address for the .bss section         */
 
+#if defined(NO_DATA_SEGMENT_IN_PSRAM) && (SLI_SI91X_MCU_ENABLE_PSRAM_SECTION_FEATURE == ENABLE)
+extern unsigned long _slpcode; /*!< Start address for the initialization
+                                      values of the .sleep_psram_driver section.            */
+extern unsigned long _scode;   /*!< Start address for the .sleep_psram_driver section     */
+extern unsigned long _ecode;   /*!< End address for the .sleep_psram_driver section       */
+#endif
+
 /*---------------------------------------------------------------------------
  * Internal References
  *---------------------------------------------------------------------------*/
@@ -206,7 +209,7 @@ void Copy_Table(void)
   for (pulDest = &_sdata; pulDest < &_edata;) {
     *(pulDest++) = *(pulSrc++);
   }
-#if defined(SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE) && (SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE == ENABLE)
+#if defined(NO_DATA_SEGMENT_IN_PSRAM) && (SLI_SI91X_MCU_ENABLE_PSRAM_SECTION_FEATURE == ENABLE)
   /* Copy the sleep PSRAM driver segment to SRAM */
   pulSrc = &_slpcode;
   for (pulDest = &_scode; pulDest < &_ecode;) {

diff --git a/components/device/silabs/si91x/mcu/drivers/service/littlefs/component/sl_si91x_littlefs.slcc b/components/device/silabs/si91x/mcu/drivers/service/littlefs/component/sl_si91x_littlefs.slcc
@@ -17,6 +17,8 @@ requires:
   - name: romdriver_qspi
 template_contribution:
   - name: littlefs_enable
-    value: true  
+    value: true
+  - name: max_flash_size
+    value: 2088960 #0x1fe000        
 provides:
   - name: sl_si91x_littlefs
diff --git a/...ts/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_common_flash_nvm3.slcc b/...ts/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_common_flash_nvm3.slcc
@@ -41,5 +41,7 @@ template_contribution:
     value: true
   - name: ram_execution
     value: true
+  - name: max_flash_size
+    value: 2088960 #0x1fe000     
 provides:
   - name: sl_si91x_common_flash_nvm3
diff --git a/...ents/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_dual_flash_nvm3.slcc b/...ents/device/silabs/si91x/mcu/drivers/service/nvm3/component/sl_si91x_dual_flash_nvm3.slcc
@@ -35,5 +35,7 @@ requires:
 template_contribution:
   - name: nvm3_enable
     value: true
+  - name: max_flash_size
+    value: 2088960 #0x1fe000       
 provides:
   - name: sl_si91x_dual_flash_nvm3
diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/bss_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/bss_segment_in_psram.slcc
@@ -7,6 +7,8 @@ category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations
 quality: production
 provides:
   - name: bss_segment_in_psram
+requires:
+  - name: wiseconnect_toolchain_psram_linker    
 template_contribution:
   - name: bss_segment_in_psram
     value: 1

diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/data_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/data_segment_in_psram.slcc
@@ -5,8 +5,13 @@ description: >
   This component puts Data segment in PSRAM memory region
 category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations
 quality: production
+define:
+  - name: NO_DATA_SEGMENT_IN_PSRAM
+    condition: [device_needs_ram_execution]
 provides:
   - name: data_segment_in_psram
+requires:
+  - name: wiseconnect_toolchain_psram_linker    
 template_contribution:
   - name: data_segment_in_psram
     value: 1

diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/heap_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/heap_segment_in_psram.slcc
@@ -7,6 +7,8 @@ category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations
 quality: production
 provides:
   - name: heap_segment_in_psram
+requires:
+  - name: wiseconnect_toolchain_psram_linker    
 template_contribution:
   - name: heap_segment_in_psram
     value: 1    

diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/stack_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/stack_segment_in_psram.slcc
@@ -7,6 +7,8 @@ category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations
 quality: production
 provides:
   - name: stack_segment_in_psram
+requires:
+  - name: wiseconnect_toolchain_psram_linker    
 template_contribution:
   - name: stack_segment_in_psram
     value: 1

diff --git a/components/device/silabs/si91x/mcu/drivers/unified_api/component/text_segment_in_psram.slcc b/components/device/silabs/si91x/mcu/drivers/unified_api/component/text_segment_in_psram.slcc
@@ -7,10 +7,10 @@ category: Device|Si91x|MCU|Peripheral|PSRAM Driver|PSRAM Linker Configurations
 quality: production
 provides:
   - name: text_segment_in_psram
+requires:
+  - name: wiseconnect_toolchain_psram_linker    
 template_contribution:
   - name: text_segment_in_psram
     value: 1
   - name: psram_linker_config_enabled
-    value: 1
-conflicts:
-  - name: device_needs_ram_execution
+    value: 1
diff --git a/components/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_plugin.slcc b/components/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_plugin.slcc
@@ -10,8 +10,10 @@ root_path: components/device/silabs/si91x/mcu/toolchain
 provides:
   - name: wiseconnect_toolchain_plugin
 template_file:
+  - path: linkerfile_psram_SoC.ld.jinja
+    condition: [wiseconnect_toolchain_psram_linker]
   - path: linkerfile_SoC.ld.jinja
-    unless: [wiseconnect_toolchain_gcc_override, wiseconnect_toolchain_custom_linker]
+    unless: [wiseconnect_toolchain_gcc_override, wiseconnect_toolchain_custom_linker, wiseconnect_toolchain_psram_linker]
 requires:
   - name: toolchain_gcc
   - name: toolchain_variant_arm
@@ -24,9 +26,12 @@ library:
     unless:
       - wiseconnect_toolchain_gcc_override
 toolchain_settings:
+  - option: linkerfile
+    value: autogen/linkerfile_psram_SoC.ld
+    condition: [wiseconnect_toolchain_psram_linker]
   - option: linkerfile
     value: autogen/linkerfile_SoC.ld
-    unless: [wiseconnect_toolchain_gcc_override, wiseconnect_toolchain_custom_linker]
+    unless: [wiseconnect_toolchain_gcc_override, wiseconnect_toolchain_custom_linker, wiseconnect_toolchain_psram_linker]
   - option: gcc_linker_option
     value: "-u _printf_float"
   - option: gcc_compiler_option

diff --git a/...nents/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_psram_linker.slcc b/...nents/device/silabs/si91x/mcu/toolchain/component/wiseconnect_toolchain_psram_linker.slcc
@@ -0,0 +1,14 @@
+id: wiseconnect_toolchain_psram_linker
+label: Toolchain support for PSRAM Linker
+package: platform
+description: >
+  Selecting this will include the PSRAM Linker component.
+category: Device|Si91x|MCU|Toolchain
+ui_hints:
+  visibility: never
+quality: production
+root_path: components/device/silabs/si91x/mcu/toolchain
+provides:
+  - name: wiseconnect_toolchain_psram_linker
+requires:
+  - name: wiseconnect_toolchain_plugin
diff --git a/components/device/silabs/si91x/mcu/toolchain/linkerfile_SoC.ld.jinja b/components/device/silabs/si91x/mcu/toolchain/linkerfile_SoC.ld.jinja
@@ -102,6 +102,10 @@
 	{%- set app_flash_size = app_flash_size - nvm_size %}
 {%- endif %}
 
+{%- if nvm3_enable or littlefs_enable %}
+	{%- set nvm3_app_max_flash_size = max_flash_size | first %}
+{%- endif %}
+
  MEMORY
  {
 {%- if flash_present %}
@@ -121,6 +125,10 @@
  }
 {%- endif %}
 
+{%- if nvm3_enable and psram_linker_config_enabled %}
+
+_last_rom_location = ORIGIN(rom);
+{%- endif %}
 {%- if psram_present and psram_linker_config_enabled %}
 
 _last_psram_location = ORIGIN(psram);
@@ -229,6 +237,11 @@ SECTIONS
 	{% endif %}
 	{% endif %}
 
+	{%- if nvm3_enable and psram_linker_config_enabled %}
+
+	__nvm3text = _last_rom_location;
+	{% endif %}
+
 	{% if psram_present and psram_linker_config_enabled and psram_powersave_handle %}
 		_slpcode = __etext;
 
@@ -561,7 +574,11 @@ SECTIONS
 
 {%- if nvm3_enable %}
   __ram_end__ = 0x{{ '%0x' % app_ram_start }} + 0x{{ '%0x' % app_ram_size }};
-  __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % app_flash_size }};
+  {%- if app_flash_size >= nvm3_app_max_flash_size %}
+   __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % nvm3_app_max_flash_size }};
+   {%- else %}
+   __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % app_flash_size }};
+  {% endif %}
 	   /* This is where we handle flash storage blocks. We use dummy sections for finding the configured
    * block sizes and then "place" them at the end of flash when the size is known. */
   .internal_storage1 (DSECT) : {
@@ -578,13 +595,19 @@ SECTIONS
   __nvm3Base = linker_nvm_begin;	
   linker_storage_begin = linker_storage_end - SIZEOF(.internal_storage1);
   linker_storage_size = SIZEOF(.internal_storage1);
+ {%- if nvm3_enable and psram_linker_config_enabled %}
+  ASSERT((linker_storage_begin >= (__nvm3text + SIZEOF(.data))), "FLASH memory overflowed !")
+ {%- else %}
   ASSERT((linker_storage_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !")
+ {%- endif %} 
 
 {%- endif %}
 
 {%- if littlefs_enable %}
 {%- if nvm3_enable %}
   __main_flash_end__ = linker_nvm_begin;
+{%- elif app_flash_size >= nvm3_app_max_flash_size %}
+  __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % nvm3_app_max_flash_size }};
 {%- else %}
   __main_flash_end__ = 0x{{ '%0x' % app_flash_start }} + 0x{{ '%0x' % app_flash_size }};
 {%- endif %}
@@ -604,7 +627,11 @@ SECTIONS
   __littlefsBase = linker_littlefs_begin;
   linker_storage2_begin = linker_storage2_end - SIZEOF(.internal_storage2);
   linker_storage2_size = SIZEOF(.internal_storage2);
+ {%- if nvm3_enable and psram_linker_config_enabled %}
+  ASSERT((linker_storage2_begin >= (__nvm3text + SIZEOF(.data))), "FLASH memory overflowed !")
+ {%- else %}
   ASSERT((linker_storage2_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !")
+ {%- endif %}
 
 {%- endif %}   
 }