Merge tag 'drm-fixes-2020-11-27-1' of git://anongit.freedesktop.org/d…

…rm/drm

Pull drm fixes from Dave Airlie:
 "Unfortunately this has a bit of thanksgiving stuffing in it, as it a
  bit larger (at least the vc4 patches) than I like at this point in
  time.

  The main thing is it has a bunch of regressions fixes for reports in
  the last couple of weeks, ast, nouveau and the amdgpu ttm init fix,
  along with the usual selection of amdgpu and i915 fixes.

  The vc4 fixes are a few but they are fixes and the nastiest one is a
  fix for when you have a 2.4Ghz Wifi and a HDMI signal with a clock in
  that range and there isn't enough shielding and interference happen
  between the two, the fix adjusts the mode clock to try and avoid the
  wifi channels in that case.

  Hopefully you can merge this between turkey slices, and next week
  should be quieter.

  ast:
   - LUT loading regression fix

  nouveau:
   - relocations regression fix

  amdgpu:
   - ttm init oops fix
   - Runtime pm fix
   - SI UVD suspend/resume fix
   - HDCP fix for headless cards
   - Sienna Cichlid golden register update

  i915:
   - Fix Perf/OA workaround register corruption (Lionel)
   - Correct a comment statement in GVT (Yan)
   - Fix GT enable/disable iterrupts, including a race condition that
     prevented GPU to go idle (Chris)
   - Free stale request on destroying the virtual engine (Chris)

  exynos:
   - config dependency fix

  mediatek:
   - unused var removal
   - horizonal front/back porch formula fix

  vc4:
   - wifi and hdmi interference fix
   - mode rejection fixes
   - use after free fix
   - cleanup some code"

* tag 'drm-fixes-2020-11-27-1' of git://anongit.freedesktop.org/drm/drm: (28 commits)
  drm/nouveau: fix relocations applying logic and a double-free
  drm/ast: Reload gamma LUT after changing primary plane's color format
  drm/amdgpu: Fix size calculation when init onchip memory
  drm/amdgpu: update golden setting for sienna_cichlid
  drm/amd/display: Avoid HDCP initialization in devices without output
  drm/i915/gt: Free stale request on destroying the virtual engine
  drm/i915/gt: Don't cancel the interrupt shadow too early
  drm/i915/gt: Track signaled breadcrumbs outside of the breadcrumb spinlock
  drm/amdgpu: fix a page fault
  drm/amdgpu: fix SI UVD firmware validate resume fail
  drm/amd/amdgpu: fix null pointer in runtime pm
  drm/i915/gt: Defer enabling the breadcrumb interrupt to after submission
  drm/i915/gvt: correct a false comment of flag F_UNALIGN
  drm/i915/perf: workaround register corruption in OATAILPTR
  drm/vc4: kms: Don't disable the muxing of an active CRTC
  drm/vc4: kms: Store the unassigned channel list in the state
  drm/exynos: depend on COMMON_CLK to fix compile tests
  drm/mediatek: dsi: Modify horizontal front/back porch byte formula
  drm/vc4: hdmi: Disable Wifi Frequencies
  dt-bindings: display: Add a property to deal with WiFi coexistence
  ...

Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml

@@ -76,6 +76,12 @@ properties:
   resets:
     maxItems: 1
 
+  wifi-2.4ghz-coexistence:
+    type: boolean
+    description: >
+      Should the pixel frequencies in the WiFi frequencies range be
+      avoided?
+
 required:
   - compatible
   - reg

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

@@ -4852,7 +4852,7 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
 	if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
 		return -ENOTSUPP;
 
-	if (ras && ras->supported)
+	if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
 		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 
 	return amdgpu_dpm_baco_enter(adev);
@@ -4871,7 +4871,7 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
 	if (ret)
 		return ret;
 
-	if (ras && ras->supported)
+	if (ras && ras->supported && adev->nbio.funcs->enable_doorbell_interrupt)
 		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 
 	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

@@ -69,10 +69,10 @@ static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
 
 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
 				    unsigned int type,
-				    uint64_t size)
+				    uint64_t size_in_page)
 {
 	return ttm_range_man_init(&adev->mman.bdev, type,
-				  false, size >> PAGE_SHIFT);
+				  false, size_in_page);
 }
 
 /**

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h

@@ -67,6 +67,7 @@ struct amdgpu_uvd {
 	unsigned		harvest_config;
 	/* store image width to adjust nb memory state */
 	unsigned		decode_image_width;
+	uint32_t                keyselect;
 };
 
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

@@ -3105,6 +3105,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_3[] =
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

@@ -277,15 +277,8 @@ static void uvd_v3_1_mc_resume(struct amdgpu_device *adev)
  */
 static int uvd_v3_1_fw_validate(struct amdgpu_device *adev)
 {
-	void *ptr;
-	uint32_t ucode_len, i;
-	uint32_t keysel;
-
-	ptr = adev->uvd.inst[0].cpu_addr;
-	ptr += 192 + 16;
-	memcpy(&ucode_len, ptr, 4);
-	ptr += ucode_len;
-	memcpy(&keysel, ptr, 4);
+	int i;
+	uint32_t keysel = adev->uvd.keyselect;
 
 	WREG32(mmUVD_FW_START, keysel);
 
@@ -550,6 +543,8 @@ static int uvd_v3_1_sw_init(void *handle)
 	struct amdgpu_ring *ring;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int r;
+	void *ptr;
+	uint32_t ucode_len;
 
 	/* UVD TRAP */
 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
@@ -571,6 +566,13 @@ static int uvd_v3_1_sw_init(void *handle)
 	if (r)
 		return r;
 
+	/* Retrieval firmware validate key */
+	ptr = adev->uvd.inst[0].cpu_addr;
+	ptr += 192 + 16;
+	memcpy(&ucode_len, ptr, 4);
+	ptr += ucode_len;
+	memcpy(&adev->uvd.keyselect, ptr, 4);
+
 	r = amdgpu_uvd_entity_init(adev);
 
 	return r;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

@@ -1041,7 +1041,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 	amdgpu_dm_init_color_mod();
 
 #ifdef CONFIG_DRM_AMD_DC_HDCP
-	if (adev->asic_type >= CHIP_RAVEN) {
+	if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
 		adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
 
 		if (!adev->dm.hdcp_workqueue)

drivers/gpu/drm/ast/ast_mode.c

@@ -742,7 +742,6 @@ static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
 	case DRM_MODE_DPMS_SUSPEND:
 		if (ast->tx_chip_type == AST_TX_DP501)
 			ast_set_dp501_video_output(crtc->dev, 1);
-		ast_crtc_load_lut(ast, crtc);
 		break;
 	case DRM_MODE_DPMS_OFF:
 		if (ast->tx_chip_type == AST_TX_DP501)
@@ -777,6 +776,21 @@ static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
 	return 0;
 }
 
+static void
+ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state)
+{
+	struct ast_private *ast = to_ast_private(crtc->dev);
+	struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc->state);
+	struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state);
+
+	/*
+	 * The gamma LUT has to be reloaded after changing the primary
+	 * plane's color format.
+	 */
+	if (old_ast_crtc_state->format != ast_crtc_state->format)
+		ast_crtc_load_lut(ast, crtc);
+}
+
 static void
 ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,
 			      struct drm_crtc_state *old_crtc_state)
@@ -830,6 +844,7 @@ ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,
 
 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
 	.atomic_check = ast_crtc_helper_atomic_check,
+	.atomic_flush = ast_crtc_helper_atomic_flush,
 	.atomic_enable = ast_crtc_helper_atomic_enable,
 	.atomic_disable = ast_crtc_helper_atomic_disable,
 };

drivers/gpu/drm/exynos/Kconfig

@@ -1,7 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-only
 config DRM_EXYNOS
 	tristate "DRM Support for Samsung SoC Exynos Series"
-	depends on OF && DRM && (ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_MULTIPLATFORM || COMPILE_TEST)
+	depends on OF && DRM && COMMON_CLK
+	depends on ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_MULTIPLATFORM || COMPILE_TEST
 	depends on MMU
 	select DRM_KMS_HELPER
 	select VIDEOMODE_HELPERS