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Upgrade mapper/router to new IR #467
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There is a new test map_test.cc that is not really a unit test but gives some guarantee as to preservation of the semantics of the circuit. It's quite basic though. My work ethics tell me to signal that the decomposition to primitives is quite untested since I haven't set mapdecompositionrulepattern in any test (so the old tests now don't make use of the finer-grained scheduling obtained by decomposing to primitives) and I haven't updated the cclight platform configurations to use new-style decompositions. See also #482 |
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Allow an iteration order that does not depend on where the statements are allocated in memory. Indeed, utils::One::operator< was used to order the keys in the map, which can change between runs.
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- New IR in place of old IR - New DDG is used in place of old scheduler - Various code improvements (e.g. return result instead of modify reference parameter) - Remove BASE_RC and MINEXTEND_RC mapper options - Really order available gates by decreasing "criticality" which was the original intent but was gonne from the code.
- create C++ version of decomposed_U tests for debugging - this test is flaky and skipped in CI - skip also the Python unitary tests in CI
A long journey through the mapper
Note: the code is still quite untested. I've done my best to check that the program works as expected, but given the number of options and complexity of the code, only proper unit testing for each part and class (e.g. AlterTest, PastTest) can give a good guarantee of functionality. This would take quite some time to implement.
I have updated the docs to signal when an option is only valid when using the minextend/minextendrc route heuristics.