fix(raise_intr): fix raise_intr to allow clearing values in mip. #82
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For external and timer interrupts, we choose to let the DUT inform the REF when there is a pending interrupt and trigger it. For these types of interrupts, we set the corresponding bit in `mip` to 1 to trigger the interrupt. Moreover, we cannot modify these bits in `mip` using the `csrrw` instruction. Therefore, after triggering the interrupt, we should also clear the corresponding bit in `mip`; otherwise, it will persist in `mip` indefinitely.
Tang-Haojin
approved these changes
Jan 3, 2025
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For external and timer interrupts from outside, we choose to let the DUT inform the REF when there is a pending interrupt and trigger it.
For these types of interrupts, we set the corresponding bit in
mipto 1 so Spike can trigger the interrupt itself.Moreover, we cannot modify these bits in
mipusing thecsrrwinstruction because the corresponding bit ofmipis non-writable.Therefore, after triggering the interrupt, we should also clear the corresponding bit in
mip; otherwise, it will persist inmipindefinitely.