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OpenXiangShan / riscv-isa-sim Public

forked from riscv-software-src/riscv-isa-sim

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feat(zvfh,zfh): add F16 support#53

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huxuan0307 merged 1 commit intodifftestOpenXiangShan/riscv-isa-sim:difftestfrom f16OpenXiangShan/riscv-isa-sim:f16Copy head branch name to clipboard

Nov 8, 2024

+1-1

Conversation Commits1 (1)Checks Files changed

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Commits on Nov 6, 2024

feat(zvfh,zfh): add F16 support
HeiHuDie
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