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fix(tdata1): CPU_XIANGSHAN do not implement hit field in mcontrol6. #46

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merged 1 commit into from
Oct 8, 2024
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fix(tdata1): CPU_XIANGSHAN do not implement hit field in mcontrol6. #46

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8 changes: 8 additions & 0 deletions riscv/triggers.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,11 @@ reg_t mcontrol6_t::tdata1_read(const processor_t * const proc) const noexcept {
tdata1 = set_field(tdata1, CSR_MCONTROL6_HIT1, hit >> 1); // MSB of 2-bit field
tdata1 = set_field(tdata1, CSR_MCONTROL6_VS, proc->extension_enabled('H') ? vs : 0);
tdata1 = set_field(tdata1, CSR_MCONTROL6_VU, proc->extension_enabled('H') ? vu : 0);
#if defined(DIFFTEST) && defined(CPU_XIANGSHAN)
tdata1 = set_field(tdata1, CSR_MCONTROL6_HIT0, 0);
#else
tdata1 = set_field(tdata1, CSR_MCONTROL6_HIT0, hit & 1); // LSB of 2-bit field
#endif
tdata1 = set_field(tdata1, CSR_MCONTROL6_SELECT, select);
tdata1 = set_field(tdata1, CSR_MCONTROL6_ACTION, action);
tdata1 = set_field(tdata1, CSR_MCONTROL6_CHAIN, chain);
Expand All @@ -339,7 +343,11 @@ void mcontrol6_t::tdata1_write(processor_t * const proc, const reg_t val, const
const reg_t maskmax6 = xlen - 1;
vs = get_field(val, CSR_MCONTROL6_VS);
vu = get_field(val, CSR_MCONTROL6_VU);
#if defined(DIFFTEST) && defined(CPU_XIANGSHAN)
hit = (hit_t)0;
#else
hit = hit_t(2 * get_field(val, CSR_MCONTROL6_HIT1) + get_field(val, CSR_MCONTROL6_HIT0)); // 2-bit field {hit1,hit0}
#endif
select = get_field(val, CSR_MCONTROL6_SELECT);
action = legalize_action(val, CSR_MCONTROL6_ACTION, CSR_MCONTROL6_DMODE(xlen));
chain = allow_chain ? get_field(val, CSR_MCONTROL6_CHAIN) : 0;
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