config: add config for misaligned memory access #36
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Currently, * Nutshell Rocket-chip does not support misaligned memory access * XiangShan supports misaligned memory access for normal load/store, but does not support vector misaligned memory access. Spike only supports enabling or disabling misaligned access for all memory access uniformly. This patch enables misaligned memory access of Spike for XiangShan, though it remains limited and not fully aligned between XiangShan and Spike.
poemonsense
approved these changes
Sep 11, 2024
lewislzh
pushed a commit
that referenced
this pull request
Dec 3, 2024
Currently, * Nutshell Rocket-chip does not support misaligned memory access * XiangShan supports misaligned memory access for normal load/store, but does not support vector misaligned memory access. Spike only supports enabling or disabling misaligned access for all memory access uniformly. This patch enables misaligned memory access of Spike for XiangShan, though it remains limited and not fully aligned between XiangShan and Spike.
lewislzh
pushed a commit
that referenced
this pull request
Dec 3, 2024
Currently, * Nutshell Rocket-chip does not support misaligned memory access * XiangShan supports misaligned memory access for normal load/store, but does not support vector misaligned memory access. Spike only supports enabling or disabling misaligned access for all memory access uniformly. This patch enables misaligned memory access of Spike for XiangShan, though it remains limited and not fully aligned between XiangShan and Spike.
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Currently,
Spike only supports enabling or disabling misaligned access for all memory access uniformly. This patch enables misaligned memory access of Spike for XiangShan, though it remains limited and not fully aligned between XiangShan and Spike.