feat(rvv): Align XS on whether vector instructions set VS dirty.

OpenXiangShan · Dec 13, 2024 · c7d7045 · c7d7045
1 parent 5032472
commit c7d7045
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Showing 6 changed files with 25 additions and 0 deletions.
diff --git a/difftest/difftest-def.h b/difftest/difftest-def.h
@@ -15,6 +15,7 @@
 
 #if defined(CPU_XIANGSHAN)
 #define CONFIG_DIFF_DEBUG_MODE
+#define CONFIG_NO_DIRTY_VS
 #define CONFIG_DIFF_RVH
 #define CONFIG_DIFF_RVV
 #define CONFIG_DIFF_ZICOND

diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h
@@ -184,6 +184,14 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
       WRITE_VSTATUS; \
     dirty_vs_state; \
   } while (0);
+#define require_vector_nodirty(alu) \
+  do { \
+    require_vector_vs; \
+    require(!P.VU.vill); \
+    if (alu && !P.VU.vstart_alu) \
+      require(P.VU.vstart->read() == 0); \
+    WRITE_VSTATUS; \
+  } while (0);
 #define require_align(val, pos) require(is_aligned(val, pos))
 #define require_noover(astart, asize, bstart, bsize) \
   require(!is_overlapped(astart, asize, bstart, bsize))

diff --git a/riscv/insns/vcpop_m.h b/riscv/insns/vcpop_m.h
@@ -1,6 +1,10 @@
 // vmpopc rd, vs2, vm
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
+#if defined(DIFFTEST) && defined(CPU_XIANGSHAN) && defined(CONFIG_NO_DIRTY_VS)
+require_vector_nodirty(true)
+#else
 require_vector(true);
+#endif
 reg_t vl = P.VU.vl->read();
 reg_t rs2_num = insn.rs2();
 require(P.VU.vstart->read() == 0);

diff --git a/riscv/insns/vfirst_m.h b/riscv/insns/vfirst_m.h
@@ -1,6 +1,10 @@
 // vmfirst rd, vs2
 require(P.VU.vsew >= e8 && P.VU.vsew <= e64);
+#if defined(DIFFTEST) && defined(CPU_XIANGSHAN) && defined(CONFIG_NO_DIRTY_VS)
+require_vector_nodirty(true)
+#else
 require_vector(true);
+#endif
 reg_t vl = P.VU.vl->read();
 reg_t rs2_num = insn.rs2();
 require(P.VU.vstart->read() == 0);

diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h
@@ -1,5 +1,9 @@
 // vfmv_f_s: rd = vs2[0] (rs1=0)
+#if defined(DIFFTEST) && defined(CPU_XIANGSHAN) && defined(CONFIG_NO_DIRTY_VS)
+require_vector_nodirty(true)
+#else
 require_vector(true);
+#endif
 require_fp;
 require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZVFH)) ||
         (P.VU.vsew == e32 && p->extension_enabled('F')) ||

diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h
@@ -1,5 +1,9 @@
 // vmv_x_s: rd = vs2[0]
+#if defined(DIFFTEST) && defined(CPU_XIANGSHAN) && defined(CONFIG_NO_DIRTY_VS)
+require_vector_nodirty(true)
+#else
 require_vector(true);
+#endif
 require(insn.v_vm() == 1);
 reg_t sew = P.VU.vsew;
 reg_t rs2_num = insn.rs2();