fix(trigger): CPU_XIANGSHAN choose to match triggers for failed sc in…

…str.
OpenXiangShan · Oct 21, 2024 · 100a0b6 · 100a0b6
1 parent 6a83d0c
commit 100a0b6
Showing 1 changed file with 7 additions and 0 deletions.
diff --git a/riscv/mmu.h b/riscv/mmu.h
@@ -297,6 +297,13 @@ class mmu_t
     }
     sim->sc_failed = false;
 
+#if defined(DIFFTEST) && defined(CPU_XIANGSHAN)
+    xlate_flags_t xlate_flags = {};
+    auto access_info = generate_access_info(addr, STORE, xlate_flags);
+    reg_t transformed_addr = access_info.transformed_vaddr;
+    check_triggers(triggers::OPERATION_STORE, transformed_addr, access_info.effective_virt);
+#endif
+
     if (have_reservation) {
       sim->is_amo = true;
       store(addr, val);