feat(TopDown): add l3Miss IO for Top-Down

* Exclude all prefetch

* Co-authored-by: Xi Chen <[email protected]>

src/main/scala/huancun/HuanCun.scala

@@ -260,6 +260,7 @@ class HuanCun(implicit p: Parameters) extends LazyModule with HasHuanCunParamete
         val robHeadPaddr = Vec(cacheParams.hartIds.length, Flipped(Valid(UInt(36.W))))
         val addrMatch = Vec(cacheParams.hartIds.length, Output(Bool()))
       }
+      val l3Miss = Output(Bool())
     })
 
     val sizeBytes = cacheParams.toCacheParams.capacity.toDouble
@@ -459,6 +460,8 @@ class HuanCun(implicit p: Parameters) extends LazyModule with HasHuanCunParamete
         t.io.debugTopDown <> io.debugTopDown
       case None => io.debugTopDown.addrMatch.foreach(_ := false.B)
     }
+
+    io.l3Miss := RegNext(slices.map(_.io.l3Miss).reduce(_ || _))
   }
 
 }

src/main/scala/huancun/Slice.scala

@@ -38,6 +38,7 @@ class Slice()(implicit p: Parameters) extends HuanCunModule {
     val ctl_req = Flipped(DecoupledIO(new CtrlReq()))
     val ctl_resp = DecoupledIO(new CtrlResp())
     val ctl_ecc = DecoupledIO(new EccInfo())
+    val l3Miss = Output(Bool())
   })
   println(s"clientBits: $clientBits")
 
@@ -657,6 +658,12 @@ class Slice()(implicit p: Parameters) extends HuanCunModule {
       io.dir_result.get := directory.io.result
     }
   )
+  io.l3Miss := Cat(ms.init.init.map { m =>
+    m.io.status.valid && m.io.status.bits.channel(0) && (
+      m.io.status.bits.reqSource === MemReqSource.CPULoadData.id.U ||
+      m.io.status.bits.reqSource === MemReqSource.CPUStoreData.id.U
+    )
+  }).orR
 
   val perfinfo = IO(Output(Vec(numPCntHc, (UInt(6.W)))))
   perfinfo := DontCare