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Update misc fixes to kunminghu branch (#170)
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* prefetch: fix tp-meta-req way width (#160)

* Directory:fix perfCounter bug, match resp_bits with right valid and replacerInfo (#161)

* chore: replace deprecated APIs (#164)

* Update the clock gating primitive for VCS (#169)

---------

Co-authored-by: Easton Man <[email protected]>
Co-authored-by: CYYYC13 <[email protected]>
Co-authored-by: Tang Haojin <[email protected]>
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@Ivyfeather @eastonman
@ruiszhang @Tang-Haojin
4 people authored Mar 20, 2024
1 parent faa6e38 commit 2becec9
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Showing 7 changed files with 34 additions and 27 deletions.
2 changes: 1 addition & 1 deletion Utility
Submodule Utility updated 6 files
+1 −1 rocket-chip
+7 −0 src/main/scala/utility/CircularQueuePtr.scala
+2 −2 src/main/scala/utility/Constantin.scala
+1 −1 src/main/scala/utility/LookupTree.scala
+2 −1 src/main/scala/utility/MIMOQueue.scala
+89 −18 src/main/scala/utility/SRAMTemplate.scala
2 changes: 1 addition & 1 deletion rocket-chip
Submodule rocket-chip updated 16 files
+3 −2 src/main/scala/diplomacy/BundleBridge.scala
+1 −2 src/main/scala/diplomacy/LazyModule.scala
+4 −7 src/main/scala/groundtest/TraceGen.scala
+1 −1 src/main/scala/jtag/JtagShifter.scala
+1 −1 src/main/scala/rocket/BTB.scala
+1 −1 src/main/scala/rocket/DCache.scala
+1 −1 src/main/scala/rocket/NBDcache.scala
+2 −2 src/main/scala/rocket/RocketCore.scala
+3 −3 src/main/scala/rocket/ScratchpadSlavePort.scala
+1 −1 src/main/scala/tilelink/AtomicAutomata.scala
+3 −4 src/main/scala/tilelink/Edges.scala
+1 −1 src/main/scala/tilelink/Fragmenter.scala
+2 −2 src/main/scala/tilelink/Fuzzer.scala
+2 −2 src/main/scala/tilelink/Metadata.scala
+2 −2 src/main/scala/util/RecordMap.scala
+1 −1 src/main/scala/util/TraceCoreInterface.scala
7 changes: 7 additions & 0 deletions src/main/resources/STD_CLKGT_func.v
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,12 @@ module STD_CLKGT_func (

assign clk_en = E | TE;

`ifdef VCS
always @(CK or clk_en) begin
if (CK == 1'b0)
clk_en_reg <= clk_en;
end
`else
`ifdef VERILATOR_5
always @(CK or clk_en) begin
if (CK == 1'b0)
Expand All @@ -20,6 +26,7 @@ module STD_CLKGT_func (
begin
clk_en_reg = clk_en;
end
`endif
`endif

assign Q = CK & clk_en_reg;
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2 changes: 1 addition & 1 deletion src/main/scala/huancun/Common.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -241,7 +241,7 @@ class TPmetaReq extends Bundle {
// FIXME: parameterize the hard code
val hartid = UInt(4.W) // max 16 harts
val set = UInt(32.W)
val way = UInt(8.W)
val way = UInt(4.W)
val wmode = Bool()
val rawData = Vec(16, UInt((36-6).W))
}
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6 changes: 3 additions & 3 deletions src/main/scala/huancun/inclusive/MSHR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr
Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(
meta.state,
BRANCH,
BRANCH)(
Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
Expand Down Expand Up @@ -392,7 +392,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr
req.fromB,
MuxLookup(
Cat(meta.state, probe_next_state),
NtoN,
NtoN)(
Seq( // TODO: optimize this
Cat(TRUNK, TRUNK) -> TtoT,
Cat(TIP, TIP) -> TtoT,
Expand Down Expand Up @@ -428,7 +428,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr
Mux(
!req_acquire,
req.param,
MuxLookup(req.param, req.param, Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT))
MuxLookup(req.param, req.param)(Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT))
)

od.size := req.size
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32 changes: 16 additions & 16 deletions src/main/scala/huancun/noninclusive/Directory.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -317,33 +317,33 @@ class Directory(implicit p: Parameters)
assert(dirReadPorts == 1)
val req_r = RegEnable(req.bits, req.fire)
XSPerfAccumulate(cacheParams, "selfdir_A_req", req_r.replacerInfo.channel(0) && resp.valid)
XSPerfAccumulate(cacheParams, "selfdir_A_hit", req_r.replacerInfo.channel(0) && resp.valid && resp.bits.self.hit)
XSPerfAccumulate(cacheParams, "selfdir_A_hit", RegNext(req_r.replacerInfo.channel(0) && resp.valid) && resp.bits.self.hit)
XSPerfAccumulate(cacheParams, "selfdir_B_req", req_r.replacerInfo.channel(1) && resp.valid)
XSPerfAccumulate(cacheParams, "selfdir_B_hit", req_r.replacerInfo.channel(1) && resp.valid && resp.bits.self.hit)
XSPerfAccumulate(cacheParams, "selfdir_B_hit", RegNext(req_r.replacerInfo.channel(1) && resp.valid) && resp.bits.self.hit)
XSPerfAccumulate(cacheParams, "selfdir_C_req", req_r.replacerInfo.channel(2) && resp.valid)
XSPerfAccumulate(cacheParams, "selfdir_C_hit", req_r.replacerInfo.channel(2) && resp.valid && resp.bits.self.hit)
XSPerfAccumulate(cacheParams, "selfdir_C_hit", RegNext(req_r.replacerInfo.channel(2) && resp.valid) && resp.bits.self.hit)

XSPerfAccumulate(cacheParams, "selfdir_dirty", resp.valid && resp.bits.self.dirty)
XSPerfAccumulate(cacheParams, "selfdir_TIP", resp.valid && resp.bits.self.state === TIP)
XSPerfAccumulate(cacheParams, "selfdir_BRANCH", resp.valid && resp.bits.self.state === BRANCH)
XSPerfAccumulate(cacheParams, "selfdir_TRUNK", resp.valid && resp.bits.self.state === TRUNK)
XSPerfAccumulate(cacheParams, "selfdir_INVALID", resp.valid && resp.bits.self.state === INVALID)
XSPerfAccumulate(cacheParams, "selfdir_dirty", RegNext(resp.valid) && resp.bits.self.dirty)
XSPerfAccumulate(cacheParams, "selfdir_TIP", RegNext(resp.valid) && resp.bits.self.state === TIP)
XSPerfAccumulate(cacheParams, "selfdir_BRANCH", RegNext(resp.valid) && resp.bits.self.state === BRANCH)
XSPerfAccumulate(cacheParams, "selfdir_TRUNK", RegNext(resp.valid) && resp.bits.self.state === TRUNK)
XSPerfAccumulate(cacheParams, "selfdir_INVALID", RegNext(resp.valid) && resp.bits.self.state === INVALID)
//val perfinfo = IO(new Bundle(){
// val perfEvents = Output(new PerfEventsBundle(numPCntHcDir))
//})
val perfinfo = IO(Output(Vec(numPCntHcDir, (UInt(6.W)))))
val perfEvents = Seq(
("selfdir_A_req ", req_r.replacerInfo.channel(0) && resp.valid ),
("selfdir_A_hit ", req_r.replacerInfo.channel(0) && resp.valid && resp.bits.self.hit),
("selfdir_A_hit ", RegNext(req_r.replacerInfo.channel(0) && resp.valid) && resp.bits.self.hit),
("selfdir_B_req ", req_r.replacerInfo.channel(1) && resp.valid ),
("selfdir_B_hit ", req_r.replacerInfo.channel(1) && resp.valid && resp.bits.self.hit),
("selfdir_B_hit ", RegNext(req_r.replacerInfo.channel(1) && resp.valid) && resp.bits.self.hit),
("selfdir_C_req ", req_r.replacerInfo.channel(2) && resp.valid ),
("selfdir_C_hit ", req_r.replacerInfo.channel(2) && resp.valid && resp.bits.self.hit),
("selfdir_dirty ", resp.valid && resp.bits.self.dirty ),
("selfdir_TIP ", resp.valid && resp.bits.self.state === TIP ),
("selfdir_BRANCH ", resp.valid && resp.bits.self.state === BRANCH ),
("selfdir_TRUNK ", resp.valid && resp.bits.self.state === TRUNK ),
("selfdir_INVALID ", resp.valid && resp.bits.self.state === INVALID ),
("selfdir_C_hit ", RegNext(req_r.replacerInfo.channel(2) && resp.valid) && resp.bits.self.hit),
("selfdir_dirty ", RegNext(resp.valid) && resp.bits.self.dirty ),
("selfdir_TIP ", RegNext(resp.valid) && resp.bits.self.state === TIP ),
("selfdir_BRANCH ", RegNext(resp.valid) && resp.bits.self.state === BRANCH ),
("selfdir_TRUNK ", RegNext(resp.valid) && resp.bits.self.state === TRUNK ),
("selfdir_INVALID ", RegNext(resp.valid) && resp.bits.self.state === INVALID ),
)

for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(perfEvents).zipWithIndex) {
Expand Down
10 changes: 5 additions & 5 deletions src/main/scala/huancun/noninclusive/MSHR.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
val replace_need_release = self_meta.state > replace_clients_perm || self_meta.dirty && isT(self_meta.state)
val replace_param = MuxLookup(
Cat(self_meta.state, replace_clients_perm),
TtoB,
TtoB)(
Seq(
Cat(BRANCH, INVALID) -> BtoN,
Cat(BRANCH, BRANCH) -> BtoB,
Expand Down Expand Up @@ -249,7 +249,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
new_self_meta.dirty := self_meta.hit && self_meta.dirty || req.dirty && isParamFromT(req.param)
new_self_meta.state := MuxLookup(
req.param,
self_meta.state,
self_meta.state)(
Seq(
TtoT -> TRUNK,
TtoB -> TIP,
Expand Down Expand Up @@ -345,7 +345,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
BRANCH
),
),
MuxLookup(self_meta.state, INVALID, Seq(
MuxLookup(self_meta.state, INVALID)(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
// if prefetch read && hit && self is Trunk
Expand Down Expand Up @@ -1107,7 +1107,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S

val probeack_param = MuxLookup( // TODO: optimize this
Cat(highest_perm, probe_next_state(highest_perm, req.param)),
NtoN,
NtoN)(
Seq(
Cat(TRUNK, TRUNK) -> TtoT,
Cat(TIP, TIP) -> TtoT,
Expand Down Expand Up @@ -1159,7 +1159,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
Mux(
!req_acquire,
req.param,
MuxLookup(req.param, req.param, Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT))
MuxLookup(req.param, req.param)(Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT))
)
od.size := req.size
od.way := meta_reg.self.way
Expand Down

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