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FPGA DFL Driver Modules
The following driver modules are integral to support for an FPGA DFL Card solution.
dfl.ko - Upstream
FPGA Device Feature List (DFL) support: Device Feature List (DFL) defines a feature list structure that creates a linked list of feature headers within the MMIO space to provide an extensible way of adding features for FPGA. Driver can walk through the feature headers to enumerate feature devices (e.g. FPGA Management Engine, Port and Accelerator Function Unit) and their private features for target FPGA devices.
dfl-afu.ko - Upstream
FPGA DFL AFU Driver: This is the driver for FPGA Accelerated Function Unit (AFU) which implements AFU and Port management features. A User AFU connects to the FPGA infrastructure via a Port. There may be more than one Port/AFU per DFL based FPGA device.
dfl-emif.ko - Upstream
FPGA DFL EMIF Driver: This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control.
dfl-fme.ko - Upstream
FPGA DFL FME Driver: The FPGA Management Engine (FME) is a feature device implemented under Device Feature List (DFL) framework. Select this option to enable the platform device driver for FME which implements all FPGA platform level management features. There shall be one FME per DFL based FPGA device.
dfl-fme-br.ko - Upstream
FPGA DFL FME Bridge Driver for FPGA Management Engine: Invokes the FPGA Bridge (fpga-bridge) class driver.
dfl-fme-mgr.ko - Upstream
FPGA DFL FME Manager Driver for FPGA Management Engine: Invokes the FPGA Manager (fpga-mgr) class driver.
dfl-fme-region.ko - Upstream
FPGA DFL FME Region Driver for FPGA Management Engine: Invokes the FPGA Region (fpga-region) class driver.
dfl-hssi.ko - Legacy design; will not be submitted upstream
FPGA DFL HSSI Driver: This is the HSSI Ethernet driver for the Intel Stratix 10 FPGA. This driver provides the ability to view and change some of the transceiver tuning parameters.
dfl-n3000-nios.ko - Upstream
FPGA DFL NIOS Driver for Intel PAC N3000: This is the driver for the N3000 Nios private feature on Intel PAC (Programmable Acceleration Card) N3000. It communicates with the embedded Nios processor to configure the retimers on the card. It also instantiates the SPI master (spi-altera) for the card's BMC (Board Management Controller).
dfl-pci.ko - Upstream
FPGA DFL PCIe Device Driver: Select this option to enable PCIe driver for PCIe-based Field-Programmable Gate Array (FPGA) solutions which implement the Device Feature List (DFL). This driver provides interfaces for userspace applications to configure, enumerate, open and access FPGA accelerators on the FPGA DFL devices, enables system level management functions such as FPGA partial reconfiguration, power management and virtualization with DFL framework and DFL feature device drivers.
fpga-bridge.ko - Upstream
FPGA Bridge Framework: Supports bridges connected between host processors and FPGAs or between FPGAs.
fpga-mgr.ko - Upstream
FPGA Configuration Framework: Provides support for configuring FPGAs from the kernel. The FPGA framework adds an FPGA manager class and FPGA manager drivers.
fpga-region.ko - Upstream
FPGA Region: FPGA Region common code. An FPGA Region controls an FPGA Manager and the FPGA Bridges associated with either a reconfigurable region of an FPGA or a whole FPGA.
intel-m10-bmc-pmci.ko - Upstream
Intel MAX 10 Board Management Controller with PMCI: PMCI-connected version of BMC driver.
intel-m10-bmc-spi.ko - Upstream
Intel MAX 10 Board Management Controller with SPI: SPI-connected version of BMC driver.
intel-m10-bmc-core.ko - Upstream
Intel MAX 10 Board Management Controller: Core code for the Intel MAX 10 board management controller. This driver provides common support for accessing the BMC. Additional drivers must be enabled in order to use the functionality of the driver.
intel-m10-bmc-log.ko - Yet to be upstreamed
Intel MAX 10 Board Management Controller Log Driver: Support for the Intel MAX 10 board management controller log in FLASH.
intel-m10-bmc-hwmon.ko - Upstream
Intel MAX10 BMC Hardware Monitoring: This driver provides support for the hardware monitoring functionality on Intel MAX10 BMC chip that is used on Intel FPGA PCIe Acceleration Cards (PAC). Its sensors monitor various telemetry data of different components on the card, e.g. board temperature, FPGA core temperature/voltage/current.
intel-m10-bmc-sec-update.ko - Upstream
Intel MAX10 BMC Secure Update driver: Secure update support for the Intel MAX10 board management controller. This is a subdriver of the Intel MAX10 board management controller (BMC) and provides support for secure updates for the BMC image, the FPGA image, the Root Entry Hashes, etc.
intel-s10-phy.ko - Legacy design; will not be submitted upstream
Intel HSSI configurable ethernet phy driver: This is the Intel HSSI configurable ethernet phy driver. It provides the ability to view and change some of the transceiver tuner parameters for a QSFP interface.
n5010-hssi.ko - Not considered upstreamable
Control Plane Driver for Silicom PAC N5010 HSSI: This driver provides control plane support for the Silicom N5010 Programmable Acceleration Card. This driver adds network interfaces for the line-side QFSP modules, supporting various control/status operations.
n5010-phy.ko - Legacy design; will not be submitted upstream
Fixed Phy Driver for Silicom PAC N5010: The n5010 card consists of a primary FPGA running the network controller, and a side-fpga running the board management controller (bmc). This driver reads status bits and controls link LEDs via the bmc.
ptp_dfl_tod.ko - Yet to be upstreamed
The FPGA DFL driver for the Intel ToD slave device. The Intel FPGA ToD IP is exposed as PTP Hardware Clock (PHC) device to the Linux PTP stack to synchronize the system clock to its ToD information using phc2sys utility of the Linux PTP stack.
qsfp-mem-dfl.ko - Legacy design; will not be submitted upstream
Memory based QSFP support: Adds a DFL driver for a QSFP controller that shadows the QSFP module's memory pages in memory.
qsfp-mem-platform.ko - Legacy design; will not be submitted upstream
Memory based QSFP support: Adds a platform driver for a QSFP controller that shadows the QSFP module's memory pages in memory.
qsfp-mem-core.ko - Legacy design; will not be submitted upstream
Memory based QSFP support: Adds the core driver code for a QSFP controller that shadows the QSFP module's memory pages in memory. This code is leveraged for both the DFL and platform versions of the qsfp-mem driver.
regmap-indirect-register.ko - Yet to be upstreamed
Support for a generic indirect-register mechanism for accessing IP register space. Note that a version of this code is currently embedded in the intel-m10-bmc-pmci driver which has been accepted upstream. We intend to switch over to this implementation after additional drivers are accepted upstream that use the same indirect register access mechanism.
regmap-spi-avmm.ko - Upstream
Register map access API - SPI AVMM support: This driver implements the regmap operations for a generic SPI master to access the registers of the spi slave chip which has an Avalon bus in it.
s10hssi.ko - Not considered upstreamable
Control Plane Driver for Stratix 10 HSSI: This driver provides control plane support for a Stratix 10 High Speed Serial Interface. The Stratix 10 High Speed Serial Interface provides a data path between the FPGA and the external QSFP interfaces. This data path does not involve packets transferred between host memory and the fpga. As such a very limited set of networking functionality is provided.
spi-altera-core.ko - Upstream
Altera SPI Controller core code: The core code for the Altera SPI Controller
spi-altera-platform.ko - Upstream
Altera SPI Controller platform driver: This is the platform driver version of the driver for the Altera SPI Controller.
spi-altera-dfl.ko - Upstream
DFL bus driver for Altera SPI Controller: This is a Device Feature List (DFL) bus driver for the Altera SPI master controller. The SPI master is connected to a SPI slave to Avalon bridge in a Intel MAX BMC.
uio-dfl.ko - Upstream
Generic DFL driver for Userspace I/O devices. It is useful to provide direct access to DFL devices from userspace. A sample userspace application using this driver is available for download in a git repository: git clone https://github.com/OPAE/opae-sdk.git It can be found at: opae-sdk/tools/libopaeuio/
8250_dfl.ko - Upstream
DFL driver for the Altera 16550 implementation of the UART