Use 4 byte spills and add issues numbers

4 byte spills is required for now, but there is a task to make it work
any size spills(#52).

include/llvm/CodeGen/TargetRegisterInfo.h

@@ -317,13 +317,13 @@ class TargetRegisterInfo : public MCRegisterInfo {
 
   /// Return the size in bytes of the stack slot allocated to hold a spilled
   /// copy of a register from class RC.
-  unsigned getSpillSize(const TargetRegisterClass &RC) const {
+  virtual unsigned getSpillSize(const TargetRegisterClass &RC) const {
     return getRegClassInfo(RC).SpillSize / 8;
   }
 
   /// Return the minimum required alignment in bytes for a spill slot for
   /// a register of this class.
-  unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
+  virtual unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
     return getRegClassInfo(RC).SpillAlignment / 8;
   }
 

lib/Target/M680x0/InstPrinter/M680x0InstPrinter.cpp

@@ -12,7 +12,7 @@
 ///
 //===----------------------------------------------------------------------===//
 
-// TODO finish printer, it does not conform to Motorola asm at all
+// TODO #33 finish printer, it does not conform to Motorola asm at all
 
 #include "M680x0InstPrinter.h"
 

lib/Target/M680x0/M680x0AsmPrinter.cpp

@@ -13,7 +13,7 @@
 ///
 //===----------------------------------------------------------------------===//
 
-// TODO make it print Motorola asm
+// TODO #33 make it print Motorola asm
 
 #include "M680x0AsmPrinter.h"
 
@@ -81,11 +81,11 @@ void M680x0AsmPrinter::EmitInstruction(const MachineInstr *MI) {
 }
 
 void M680x0AsmPrinter::EmitFunctionBodyStart() {
-  // TODO
+  // TODO #33
 }
 
 void M680x0AsmPrinter::EmitFunctionBodyEnd() {
-  // TODO
+  // TODO #33
 }
 
 void M680x0AsmPrinter::EmitStartOfAsmFile(Module &M) {

lib/Target/M680x0/M680x0CallingConv.h

@@ -35,7 +35,7 @@ class M680x0CCState : public CCState {
 };
 
 /// NOTE this function is used to select registers for formal arguments and call
-/// TODO Need to assigne all the pointers first
+/// TODO #34 Need to assigne all the pointers first
 inline bool CC_M680x0_Any_AssignToReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
                                       CCValAssign::LocInfo &LocInfo,
                                       ISD::ArgFlagsTy &ArgFlags,
@@ -53,7 +53,7 @@ inline bool CC_M680x0_Any_AssignToReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
       M680x0::D1,
   };
 
-  // SHIT rewrite this
+  // SHIT #34 rewrite this
   // NOTE This is probably wrong
   auto I = CCInfo.F.arg_begin();
   int No = ValNo;

lib/Target/M680x0/M680x0CallingConv.td

@@ -14,6 +14,8 @@
 ///
 //===----------------------------------------------------------------------===//
 
+// TODO #35 Verify C convention follows SysV M68K ABI
+
 class CCIfSubtarget<string F, CCAction A>
     : CCIf<!strconcat("static_cast<const M680X0Subtarget&>"
                        "(State.getMachineFunction().getSubtarget()).", F), A>;
@@ -36,7 +38,7 @@ def RetCC_M680x0_C : CallingConv<[
 ]>;
 
 /// M680x0 fastcc return convention.
-/// TODO:
+/// TODO #36
 /// This convention allows to return upto 16 bytes in registers which can be
 /// split among 16 1-byte values or used for a single 16-byte value.
 def RetCC_M680x0_Fast : CallingConv<[
@@ -73,7 +75,7 @@ def CC_M680x0_Fast : CallingConv<[
   CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
 
   /// The 'nest' parameter, if any, is passed in A1.
-  CCIfNest<CCAssignToReg<[A1]>>, // FIXME is this correct?
+  CCIfNest<CCAssignToReg<[A1]>>, // FIXME #2 is this correct?
 
   /// Since M680x0 uses %An for pointers and we want them be passed in regs
   /// too we have to use custom function.
@@ -88,7 +90,7 @@ def CC_M680x0_C : CallingConv<[
   CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
 
   /// The 'nest' parameter, if any, is passed in A1.
-  CCIfNest<CCAssignToReg<[A1]>>, // FIXME is this correct?
+  CCIfNest<CCAssignToReg<[A1]>>, // FIXME #2 is this correct?
 
   /// Use registers only if 'inreg' used and the call is not vararg
   CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[D0, D1]>>>>,

lib/Target/M680x0/M680x0ExpandPseudo.cpp

@@ -80,7 +80,7 @@ bool M680x0ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
   switch (Opcode) {
   default:
     return false;
-    /// TODO would be nice to infer all these parameters
+    /// TODO #37 would be nice to infer all these parameters
 
   case M680x0::MOVXd16d8:
     return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8);
@@ -257,7 +257,7 @@ bool M680x0ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
         // MIB = BuildMI(MBB, MBBI, DL, TII->get(M680x0::RTD)).addImm(StackAdj);
       } else {
         // Copy PC from stack to a free address(A0 or A1) register
-        // TODO check if it is really free
+        // TODO #38 check if it is really free
         BuildMI(MBB, MBBI, DL, TII->get(M680x0::MOV32aj), M680x0::A1)
             .addReg(M680x0::SP);
 

lib/Target/M680x0/M680x0FrameLowering.cpp

@@ -49,7 +49,7 @@ bool M680x0FrameLowering::hasFP(const MachineFunction &MF) const {
          TRI->needsStackRealignment(MF);
 }
 
-// FIXME not only pushes....
+// FIXME #6 not only pushes....
 bool M680x0FrameLowering::hasReservedCallFrame(
     const MachineFunction &MF) const {
   return !MF.getFrameInfo().hasVarSizedObjects() &&
@@ -115,7 +115,7 @@ int M680x0FrameLowering::getFrameIndexReference(const MachineFunction &MF,
       assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0);
       return Offset + StackSize;
     }
-    // FIXME: Support tail calls
+    // FIXME: #7 Support tail calls
   } else {
     if (!HasFP)
       return Offset + StackSize;
@@ -424,7 +424,7 @@ int M680x0FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
     MBB.erase(PI);
     if (!doMergeWithPrevious)
       MBBI = NI;
-    // TODO check this
+    // TODO #40 check this
     // } else if (Opc == M680x0::LEA32p &&
     //            PI->getOperand(0).getReg() == StackPtr &&
     //            PI->getOperand(2).getReg() == StackPtr) {
@@ -447,7 +447,7 @@ MachineInstrBuilder M680x0FrameLowering::BuildStackAdjustment(
     const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
   assert(Offset != 0 && "zero offset stack adjustment requested");
 
-  // ??? in the original code for M680x0 Atom uses lea to adjust stack as an
+  // TODO #8 in the original code for M680x0 Atom uses lea to adjust stack as an
   // optimization, can be be this applied for M680x0?
 
   bool IsSub = Offset < 0;
@@ -457,7 +457,7 @@ MachineInstrBuilder M680x0FrameLowering::BuildStackAdjustment(
   MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
                                .addReg(StackPtr)
                                .addImm(AbsOffset);
-  // FIXME ATM there is no CCR in these inst
+  // FIXME #9 ATM there is no CCR in these inst
   MI->getOperand(3).setIsDead(); // The CCR implicit def is dead.
   return MI;
 }
@@ -688,7 +688,7 @@ void M680x0FrameLowering::emitPrologue(MachineFunction &MF,
       emitCalleeSavedFrameMoves(MBB, MBBI, DL);
   }
 
-  // TODO interrupts...
+  // TODO #10 interrupts...
   // M680x0 Interrupt handling function cannot assume anything about the
   // direction flag (DF in CCR register). Clear this flag by creating "cld"
   // instruction in each prologue of interrupt handler function.

lib/Target/M680x0/M680x0FrameLowering.h

@@ -167,7 +167,7 @@ class M680x0FrameLowering : public TargetFrameLowering {
   void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
                     int64_t NumBytes, bool InEpilogue) const;
 
-  /// TODO
+  /// TODO #39
   /// Order the symbols in the local stack.
   /// We want to place the local stack objects in some sort of sensible order.
   /// The heuristic we use is to try and pack them according to static number

lib/Target/M680x0/M680x0ISelDAGToDAG.cpp

@@ -43,7 +43,7 @@ namespace {
 
 /// isInt - Checks if an integer fits into the given bit width.
 /// non-templated version
-/// FIXME move it somewhere
+/// FIXME #11 move it somewhere
 inline bool isInt(unsigned N, int64_t x) {
   return N >= 64 ||
          (-(INT64_C(1) << (N - 1)) <= x && x < (INT64_C(1) << (N - 1)));
@@ -382,10 +382,7 @@ bool M680x0DAGToDAGISel::matchAddressBase(SDValue N,
   return true;
 }
 
-/// TODO
-/// Have no idea how it is node with M680x0 ATM
-/// Here is some description:
-/// https://lists.debian.org/debian-68k/2007/11/msg00071.html
+/// TODO #41 Add TLS support
 bool M680x0DAGToDAGISel::matchLoadInAddress(LoadSDNode *N,
                                             M680x0ISelAddressMode &AM) {
   // SDValue Address = N->getOperand(1);
@@ -426,7 +423,7 @@ bool M680x0DAGToDAGISel::matchAddressRecursively(SDValue N,
   // into it.  Instead of handling this in every case, we handle it here.
   // PC relative addressing: %PC + 16-bit displacement!
   if (AM.isPCRelative()) {
-    // FIXME: JumpTable and ExternalSymbol address currently don't like
+    // FIXME #12 JumpTable and ExternalSymbol address currently don't like
     // displacements.  It isn't very important, but this should be fixed for
     // consistency.
     // if (!(AM.ES || AM.MCSym) && AM.JT != -1)
@@ -498,7 +495,7 @@ bool M680x0DAGToDAGISel::matchAddress(SDValue N, M680x0ISelAddressMode &AM) {
 
   // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
   // a smaller encoding and avoids a scaled-index.
-  // TODO make sure it is an indexed mode
+  // TODO #13 make sure it is an indexed mode
   // if (AM.Scale == 2 &&
   //     AM.BaseType == M680x0ISelAddressMode::RegBase &&
   //     AM.BaseReg.getNode() == nullptr) {
@@ -508,8 +505,8 @@ bool M680x0DAGToDAGISel::matchAddress(SDValue N, M680x0ISelAddressMode &AM) {
 
   // Post-processing: Convert foo to foo(%pc), even in non-PIC mode,
   // because it has a smaller encoding.
-  // TODO: Which other code models can use this?
-  // FIXME this must be done only if PC* modes are currently being matched
+  // TODO #13 Which other code models can use this?
+  // FIXME #13 this must be done only if PC* modes are currently being matched
   // if (TM.getCodeModel() == CodeModel::Small &&
   //     Subtarget->is64Bit() &&
   //     AM.Scale == 1 &&