Library containing various Systemverilog IPs
see: here
IPs have the following file and directory structure:
- bd : Verilog wrappers for IPs. Vivado IP packager cannot package IPs with Systemverilog top level.
- constraints : .xdc constraint files
- doc : Documentation
- src : HDL sources
- tb : SVUnit test benches
- xgui : Vivado IP packager tcl script
- component.xml : IP-XACT description of IP generated by Vivado
# Activate python venv
.venv/Scripts/Activate.ps1
# Navigate to sim dir
cd tb/sim
# Run in Console Mode
runsvunit -s modelsim -o sim -f sim.f
# Run in Gui Mode
RunSVUnit -s modelsim -o sim -f sim.f -r="-gui -voptargs=+acc"