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QUASAR 2.0 Final
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​Laraib Khan committed Apr 9, 2021
1 parent 0e91028 commit a263903
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Showing 13 changed files with 154 additions and 368 deletions.
5 changes: 4 additions & 1 deletion design/src/main/scala/dec/dec.scala
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Expand Up @@ -121,7 +121,10 @@ class dec extends Module with param with RequireAsyncReset{
val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
val dec_tlu_trace_disable = WireInit(Bool(),0.B)

// val dec_i0_bp_fa_index = WireInit(UInt(log2Ceil(BTB_SIZE).W),0.U)
//val dec_debug_valid_d = WireInit(Bool(),0.B)



//--------------------------------------------------------------------------//
val instbuff = Module(new dec_ib_ctl)
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120 changes: 6 additions & 114 deletions design/src/main/scala/dec/dec_tlu_ctl.scala
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29 changes: 1 addition & 28 deletions design/src/main/scala/dma_ctrl.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,6 @@
import chisel3._
import chisel3.util._
import include._
//import dbg._
import scala.collection._
import lib._

Expand Down Expand Up @@ -69,32 +68,6 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
val dma_address_error = WireInit(Bool(), false.B)
val dma_alignment_error = WireInit(Bool(), false.B)

// val fifo_cmd_en = (0 until DEPTH).map(i=>((bus_cmd_sent & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1))) & (WrPtr === i.U).asUInt()).reverse.reduce(Cat(_,_))
//
// val fifo_data_en = (0 until DEPTH).map(i => ((((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) &
// (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) |
// (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) |
// (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
//
// val fifo_pend_en = (0 until DEPTH).map(i => ((io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
//
// val dma_dbg_cmd_error = WireInit(Bool(), false.B)
//
// val fifo_error_en = (0 until DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) &
// (i.U === RdPtr)) | ((io.dccm_dma_rvalid & io.dccm_dma_ecc_error) & (i.U === io.dccm_dma_rtag)) |
// ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
// val fifo_error_in = Wire(Vec(DEPTH, UInt(2.W)))
// val fifo_error = Wire(Vec(DEPTH, UInt(2.W)))
// val fifo_error_bus_en = (0 until DMA_BUF_DEPTH).map(i=>(((fifo_error_in(i).orR & fifo_error_en(i)) | fifo_error(i).orR) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
// val fifo_done_en = (0 until DMA_BUF_DEPTH).map(i=>(((fifo_error(i).orR | fifo_error_en(i) | ((io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write)) & (i.U === RdPtr)) |
// (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
// val fifo_done = WireInit(UInt(DEPTH.W), 0.U)
// val fifo_done_bus_en = (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
// val bus_rsp_sent = WireInit(Bool(), false.B)
// val bus_posted_write_done = WireInit(Bool(), false.B)
// val RspPtr = WireInit(UInt(DEPTH_PTR.W), 0.U)
// val fifo_reset = (0 until DMA_BUF_DEPTH).map(i=>((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr)).asUInt()).reverse.reduce(Cat(_,_))
// fifo_error_in := (0 until DMA_BUF_DEPTH).map(i=>Mux(io.dccm_dma_rvalid & (io.dccm_dma_rtag===i.U), Cat(0.U(1.W),io.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (io.iccm_dma_rtag===i.U), Cat(0.U(1.W),io.iccm_dma_ecc_error), Cat(dma_address_error | dma_alignment_error | dma_dbg_cmd_error, dma_alignment_error))))
val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)

val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
Expand Down Expand Up @@ -155,7 +128,7 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
val fifo_posted_write = (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
val fifo_dbg = (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_))

val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))//VecInit.tabulate(DMA_BUF_DEPTH)(i =>rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
(0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W),0.U)
val bus_cmd_mid = WireInit(UInt(DMA_BUS_ID.W),0.U)
Expand Down
19 changes: 0 additions & 19 deletions design/src/main/scala/exu/exu_mul_ctl.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -23,14 +23,6 @@ class exu_mul_ctl extends Module with RequireAsyncReset with lib {
val low_x = WireInit(0.U(1.W))

// *** Start - BitManip ***

// val bitmanip_sel_d = WireInit(Bool(),0.B)
// val bitmanip_sel_x = WireInit(Bool(),0.B)
// val bitmanip_d = WireInit(UInt(32.W),0.U)
// val bitmanip_x = WireInit(UInt(32.W),0.U)



// ZBE
val ap_bext = WireInit(Bool(),0.B)
val ap_bdep = WireInit(Bool(),0.B)
Expand Down Expand Up @@ -188,14 +180,6 @@ class exu_mul_ctl extends Module with RequireAsyncReset with lib {
// return x;
// }


// logic [31:0] gorc1_d;
// logic [31:0] gorc2_d;
// logic [31:0] gorc4_d;
// logic [31:0] gorc8_d;
// logic [31:0] gorc_d;
//

val gorc1_d = ( Fill(32,io.rs2_in(0)) & Range(0, 31, 2).map(i=> Cat(io.rs1_in(i),io.rs1_in(i+1))).reverse.reduce(Cat(_,_)) ) | io.rs1_in

val gorc2_d = ( Fill(32,io.rs2_in(1)) & Range(0, 31, 4).map(i=> Cat(gorc1_d(i+1,i),gorc1_d(i+1+2,i+2))).reverse.reduce(Cat(_,_)) ) | gorc1_d
Expand Down Expand Up @@ -378,9 +362,6 @@ class exu_mul_ctl extends Module with RequireAsyncReset with lib {
ap_crc32c_w -> crc32c_wd(32)(31,0) ,
ap_bfp -> bfp_result_d(31,0) ))



//rvdffe #(33) i_bitmanip_ff (.*, .clk(clk), .din({bitmanip_sel_d,bitmanip_d[31:0]}), .dout({bitmanip_sel_x,bitmanip_x[31:0]}), .en(bit_x_enable));
val bitmanip_sel_x = rvdffe(bitmanip_sel_d,bit_x_enable,clock,io.scan_mode)
val bitmanip_x = rvdffe(bitmanip_d,bit_x_enable,clock,io.scan_mode)

Expand Down
16 changes: 1 addition & 15 deletions design/src/main/scala/ifu/ifu_aln_ctl.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -14,22 +14,8 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
val ic_access_fault_type_f = Input(UInt(2.W)) // Type of access fault occured
val dec_i0_decode_d = Input(Bool())
val dec_aln = new dec_aln()
// val ifu_i0_valid = Output(Bool())
// val ifu_i0_icaf = Output(Bool())
// val ifu_i0_icaf_type = Output(UInt(2.W))
// val ifu_i0_icaf_second = Output(Bool())
// val ifu_i0_dbecc = Output(Bool())
// val ifu_i0_instr = Output(UInt(32.W))
// val ifu_i0_pc = Output(UInt(31.W))
// val ifu_i0_pc4 = Output(Bool())
val ifu_bp_fa_index_f = Vec(2, Input(UInt(log2Ceil(BTB_SIZE).W)))
// val i0_brp = Output(Valid(new br_pkt_t()))
// val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
// val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
// val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_i0_fa_index = Output(UInt(log2Ceil(BTB_SIZE).W))
// val ifu_pmu_instr_aligned = Output(Bool())
// val ifu_i0_cinst = Output(UInt(16.W))
val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
val ifu_bp_btb_target_f = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
val ifu_bp_poffset_f = Input(UInt(12.W)) // Offset to the current PC for branch
Expand Down Expand Up @@ -513,4 +499,4 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
}
//object Aligner extends App {
// (new chisel3.stage.ChiselStage).emitVerilog(new ifu_aln_ctl())
//}
//}
111 changes: 54 additions & 57 deletions design/src/main/scala/ifu/ifu_bp_ctl.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -438,60 +438,60 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset {
btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i)))
btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
}
// if(BTB_FULLYA){
// val fetch_mp_collision_f = WireInit(Bool(),init = false.B)
// val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B)
//
// // Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks
// // Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry.
// val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U
//
//
// // val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
// // val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
// // val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool()))
// val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W)))
// btbdata := btbdata.map(i=> 0.U)
// val hit0 = WireInit(UInt(1.W) ,init = 0.U)
// val hit1 = WireInit(UInt(1.W) ,init = 0.U)
//
// // btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i)))
// // val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
// // val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
//
// // hit unless we are also writing this entry at the same time
// val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U))
// val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U))
// // Mux out the 2 potential branches
// btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_))
// btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_))
// val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U))
//
// vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U)
// way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f)
// wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) |
// ((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_))
// btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode))
//
// io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U)
// io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U)
//
// val btb_used_reset = btb_used.andR()
// val btb_used_ns = Mux1H(Seq(
// vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)),
// vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)),
// (exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)),
// btb_used_reset.asBool -> Fill(BTB_SIZE,0.U),
// (!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))),
// !(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used
// ))
// val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb
// btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode)
// }
if(BTB_FULLYA){
val fetch_mp_collision_f = WireInit(Bool(),init = false.B)
val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B)

// Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks
// Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry.
val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U


fetch_mp_collision_f := ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
fetch_mp_collision_p1_f := ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool()))
val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W)))
btbdata := btbdata.map(i=> 0.U)
val hit0 = WireInit(UInt(1.W) ,init = 0.U)
val hit1 = WireInit(UInt(1.W) ,init = 0.U)

btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i)))
//btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
//btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))

// hit unless we are also writing this entry at the same time
val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U))
val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U))
// Mux out the 2 potential branches
btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_))
btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_))
val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U))

vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U)
way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f)
wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) |
((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_))
btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode))

io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U)
io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U)

val btb_used_reset = btb_used.andR()
val btb_used_ns = Mux1H(Seq(
vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)),
vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)),
(exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)),
btb_used_reset.asBool -> Fill(BTB_SIZE,0.U),
(!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))),
!(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used
))
val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb
btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode)
}

val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool())))

Expand Down Expand Up @@ -530,6 +530,3 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset {
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i)))
bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i)))
}
//object bp_MAIN extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_bp_ctl()))
//}
12 changes: 1 addition & 11 deletions design/src/main/scala/lsu/lsu.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,6 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val dec_tlu_mrac_ff = Input(UInt(32.W))

//Outputs
// val lsu_result_m = Output(UInt(32.W))
val lsu_result_corr_r = Output(UInt(32.W))
val lsu_load_stall_any = Output(Bool())
val lsu_store_stall_any = Output(Bool())
Expand All @@ -56,22 +55,13 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val dma_mem_tag_m = WireInit(0.U(3.W))
val lsu_raw_fwd_lo_r = WireInit(0.U(1.W))
val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
// val lsu_busm_clken = WireInit(0.U(1.W))
val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W))
// val lsu_addr_d = WireInit(0.U(32.W))
// val lsu_addr_m = WireInit(0.U(32.W))
// val lsu_addr_r = WireInit(0.U(32.W))
// val end_addr_d = WireInit(0.U(32.W))
// val end_addr_m = WireInit(0.U(32.W))
// val end_addr_r = WireInit(0.U(32.W))
val lsu_busreq_r = WireInit(Bool(),false.B)
val ldst_dual_d = WireInit(Bool(),false.B)
val ldst_dual_m = WireInit(Bool(),false.B)
val ldst_dual_r = WireInit(Bool(),false.B)

val lsu_lsc_ctl = Module(new lsu_lsc_ctl())
// io.lsu_exu.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
// io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data
io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r
val dccm_ctl = Module(new lsu_dccm_ctl())
val stbuf = Module(new lsu_stbuf())
Expand Down Expand Up @@ -354,4 +344,4 @@ class lsu extends Module with RequireAsyncReset with param with lib {
}
object lsu_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
}
}
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