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Add ram chip Esp psram32 (#647)
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Misca1234 authored and poeschlr committed Dec 30, 2018
1 parent 695c388 commit b5bb898
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6 changes: 6 additions & 0 deletions Memory_RAM.dcm
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,12 @@ K memory SRAM
F http://www.alliancememory.com/pdf/AS6C1616(1).pdf
$ENDCMP
#
$CMP ESP-PSRAM32
D 32 Mbit serial pseudo SRAM device organized as 4Mx8 bits, 1.8 VCC, SOIC8 (SOP8)
K 32 Mbit serial pseudo SRAM
F https://www.espressif.com/sites/default/files/documentation/esp-psram32_datasheet_en.pdf
$ENDCMP
#
$CMP H5AN8G8NAFR-UHC
D 8Gb CMOS Double Data Rate IV Synchronous RAM
K DDR4 DRAM
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71 changes: 47 additions & 24 deletions Memory_RAM.lib
Original file line number Diff line number Diff line change
Expand Up @@ -3,13 +3,13 @@ EESchema-LIBRARY Version 2.4
#
# 628128
#
DEF 628128 U 0 40 Y Y 1 F N
F0 "U" 50 0 50 H V C CNN
F1 "628128" 300 -1200 50 H V C CNN
DEF 628128 U 0 20 Y Y 1 F N
F0 "U" -350 1150 50 H V C CNN
F1 "628128" 250 1150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -400 1100 400 -1100 0 1 0 N
S -400 1100 400 -1100 0 1 10 f
X GND 16 0 -1100 0 U 50 50 0 0 W N
X VCC 32 0 1100 0 D 50 50 0 0 W N
X A2 10 -700 850 300 R 50 50 1 1 I
Expand Down Expand Up @@ -110,7 +110,7 @@ ENDDEF
#
# AS6C1616
#
DEF AS6C1616 U 0 40 Y Y 1 F N
DEF AS6C1616 U 0 20 Y Y 1 F N
F0 "U" -350 1250 50 H V C CNN
F1 "AS6C1616" 250 -1250 50 H V C CNN
F2 "Package_SO:TSOP-I-48_18.4x12mm_P0.5mm" 1050 -1350 50 H I C CNN
Expand Down Expand Up @@ -173,7 +173,7 @@ ENDDEF
#
# CY7C199
#
DEF CY7C199 U 0 40 Y Y 1 F N
DEF CY7C199 U 0 20 Y Y 1 F N
F0 "U" -450 1100 50 H V L CNN
F1 "CY7C199" 150 1100 50 H V L CNN
F2 "" 0 0 50 H I C CNN
Expand All @@ -193,14 +193,14 @@ X D5 17 600 400 150 L 50 50 1 1 T
X D6 18 600 300 150 L 50 50 1 1 T
X D7 19 600 200 150 L 50 50 1 1 T
X A6 2 -600 300 150 R 50 50 1 1 I
X ~CE~ 20 -600 -700 150 R 50 50 1 1 I I
X ~CE~ 20 -600 -700 150 R 50 50 1 1 I
X A0 21 -600 900 150 R 50 50 1 1 I
X ~OE~ 22 -600 -800 150 R 50 50 1 1 I I
X ~OE~ 22 -600 -800 150 R 50 50 1 1 I
X A1 23 -600 800 150 R 50 50 1 1 I
X A2 24 -600 700 150 R 50 50 1 1 I
X A3 25 -600 600 150 R 50 50 1 1 I
X A4 26 -600 500 150 R 50 50 1 1 I
X ~WE~ 27 -600 -900 150 R 50 50 1 1 I I
X ~WE~ 27 -600 -900 150 R 50 50 1 1 I
X A7 3 -600 200 150 R 50 50 1 1 I
X A8 4 -600 100 150 R 50 50 1 1 I
X A9 5 -600 0 150 R 50 50 1 1 I
Expand All @@ -211,6 +211,29 @@ X A13 9 -600 -400 150 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# ESP-PSRAM32
#
DEF ESP-PSRAM32 U 0 20 Y Y 1 F N
F0 "U" 150 450 50 H V C CNN
F1 "ESP-PSRAM32" -50 -450 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -600 50 H I C CNN
F3 "" -400 500 50 H I C CNN
$FPLIST
SOIC*3.9x4.9mm?P1.27mm*
$ENDFPLIST
DRAW
S -300 400 300 -400 0 1 10 f
X ~CE 1 400 300 100 L 50 50 1 1 I
X SO/SIO 2 400 -200 100 L 50 50 1 1 O
X SIO2 3 400 0 100 L 50 50 1 1 B
X VSS 4 -100 -500 100 U 50 50 1 1 W
X SI/SIO 5 400 -100 100 L 50 50 1 1 I
X SCLK 6 400 200 100 L 50 50 1 1 O
X SIO3 7 400 100 100 L 50 50 1 1 B
X VCC 8 -100 500 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# H5AN8G8NAFR-UHC
#
DEF H5AN8G8NAFR-UHC U 0 20 Y Y 1 F N
Expand Down Expand Up @@ -307,13 +330,13 @@ ENDDEF
#
# IDT7027_TQ100
#
DEF IDT7027_TQ100 U 0 30 Y Y 1 F N
F0 "U" 0 2250 50 H V C CNN
F1 "IDT7027_TQ100" 50 -2300 50 H V C CNN
DEF IDT7027_TQ100 U 0 20 Y Y 1 F N
F0 "U" -550 2250 50 H V C CNN
F1 "IDT7027_TQ100" 500 2250 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -600 2200 600 -2200 0 1 0 N
S -600 2200 600 -2200 0 1 10 f
X A9L 1 -900 1200 300 R 50 50 1 1 I
X LBL 10 -900 -1800 300 R 50 50 1 1 I I
X A8L 100 -900 1300 300 R 50 50 1 1 I
Expand Down Expand Up @@ -411,13 +434,13 @@ ENDDEF
#
# IDT7132
#
DEF IDT7132 U 0 40 Y Y 1 F N
DEF IDT7132 U 0 20 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "IDT7132" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -600 -1400 600 1400 0 1 0 N
S -600 -1400 600 1400 0 1 10 f
X /CEL 1 -900 1200 300 R 50 50 1 1 I
X A4L 10 -900 300 300 R 50 50 1 1 I
X A5L 11 -900 200 300 R 50 50 1 1 I
Expand Down Expand Up @@ -471,13 +494,13 @@ ENDDEF
#
# IDT71V65903S
#
DEF IDT71V65903S U 0 40 Y Y 1 F N
DEF IDT71V65903S U 0 20 Y Y 1 F N
F0 "U" 0 3500 50 H V C CNN
F1 "IDT71V65903S" 0 -3500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -450 3450 450 -3450 0 1 0 N
S -450 3450 450 -3450 0 1 10 f
X A8 A10 -700 2600 250 R 50 50 1 1 I
X A10 A11 -700 2400 250 R 50 50 1 1 I
X A7 A2 -700 2700 250 R 50 50 1 1 I
Expand Down Expand Up @@ -607,20 +630,20 @@ ENDDEF
#
# IDT7201
#
DEF IDT7201 U 0 40 Y Y 1 F N
F0 "U" 0 100 50 H V C CNN
F1 "IDT7201" 0 -100 50 H V C CNN
DEF IDT7201 U 0 20 Y Y 1 F N
F0 "U" -350 800 50 H V C CNN
F1 "IDT7201" 250 800 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS IDT7202
DRAW
S -400 -750 400 750 0 1 0 N
S -400 -750 400 750 0 1 10 f
X WR 1 -700 650 300 R 50 50 1 1 I I
X Q1 10 700 450 300 L 50 50 1 1 T
X Q2 11 700 350 300 L 50 50 1 1 T
X Q3 12 700 250 300 L 50 50 1 1 T
X Q8 13 700 -250 300 L 50 50 1 1 T
X VSS 14 0 -1000 250 U 50 50 1 1 I
X VSS 14 0 -1000 250 U 50 50 1 1 W
X RD 15 700 650 300 L 50 50 1 1 I I
X Q4 16 700 150 300 L 50 50 1 1 T
X Q5 17 700 50 300 L 50 50 1 1 T
Expand All @@ -635,7 +658,7 @@ X D7 24 -700 -150 300 R 50 50 1 1 I
X D6 25 -700 -50 300 R 50 50 1 1 I
X D5 26 -700 50 300 R 50 50 1 1 I
X D4 27 -700 150 300 R 50 50 1 1 I
X VCC 28 0 1000 250 D 50 50 1 1 I
X VCC 28 0 1000 250 D 50 50 1 1 W
X D3 3 -700 250 300 R 50 50 1 1 I
X D2 4 -700 350 300 R 50 50 1 1 I
X D1 5 -700 450 300 R 50 50 1 1 I
Expand Down Expand Up @@ -692,7 +715,7 @@ ENDDEF
#
# IS42S16400J-xC
#
DEF IS42S16400J-xC U 0 40 Y Y 1 F N
DEF IS42S16400J-xC U 0 20 Y Y 1 F N
F0 "U" -600 1250 50 H V C CNN
F1 "IS42S16400J-xC" -600 -1250 50 H V C CNN
F2 "Package_SO:TSOP-II-54_10.16x22.22mm_P0.8mm" 0 0 50 H I C CNN
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