more processors

Signed-off-by: Slice <[email protected]>
CloverHackyColor · Dec 6, 2024 · 286a4f3 · 286a4f3
1 parent 788654c
commit 286a4f3
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Showing 5 changed files with 29 additions and 6 deletions.
diff --git a/Include/IndustryStandard/ProcessorInfo.h b/Include/IndustryStandard/ProcessorInfo.h
@@ -204,7 +204,9 @@ enum {
 #define CPU_MODEL_RAPTORLAKE     0xB7  /* 13h Raptor Lake */
 #define CPU_MODEL_RAPTORLAKE_B   0xBF  /* 13h Raptor Lake, i5-13400h */
 #define CPU_MODEL_METEORLAKE     0xAA  /* 14h Meteor Lake */
-#define CPU_MODEL_ARROWLAKE		 0xC6
+#define CPU_MODEL_ARROWLAKE		 0xC6  /* 15h Arrow Lake */
+#define CPU_MODEL_ARROWLAKE_X	 0xC5  /* 15h Arrow Lake */
+#define CPU_MODEL_ARROWLAKE_U	 0xB5  /* 15h Arrow Lake */
 
 #define CPU_SOCKET_UNKNOWN  0x02
 #define CPU_SOCKET_PGA478   0x0F

diff --git a/OpenCorePkg b/OpenCorePkg
diff --git a/rEFIt_UEFI/Platform/StateGenerator.cpp b/rEFIt_UEFI/Platform/StateGenerator.cpp
@@ -283,6 +283,8 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
           case CPU_MODEL_RAPTORLAKE:
           case CPU_MODEL_METEORLAKE:
           case CPU_MODEL_ARROWLAKE:
+          case CPU_MODEL_ARROWLAKE_X:
+          case CPU_MODEL_ARROWLAKE_U:
           {
             maximum.Control.Control = RShiftU64(AsmReadMsr64(MSR_PLATFORM_INFO), 8) & 0xff;
             if (gSettings.ACPI.SSDT.MaxMultiplier) {
@@ -358,6 +360,8 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
                     (gCPUStructure.Model == CPU_MODEL_RAPTORLAKE_B) ||
                     (gCPUStructure.Model == CPU_MODEL_METEORLAKE) ||
 					(gCPUStructure.Model == CPU_MODEL_ARROWLAKE  ) ||
+					(gCPUStructure.Model == CPU_MODEL_ARROWLAKE_X  ) ||
+					(gCPUStructure.Model == CPU_MODEL_ARROWLAKE_U  ) ||
                     (gCPUStructure.Model == CPU_MODEL_COMETLAKE_S) ||
                     (gCPUStructure.Model == CPU_MODEL_COMETLAKE_Y) ||
                     (gCPUStructure.Model == CPU_MODEL_COMETLAKE_U)) {
@@ -379,7 +383,7 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
                 p_states_count++;
               }
             }
-            break;//case CPU_MODEL_ARROWLAKE:
+            break;
           }
           default:
             MsgLog ("Unsupported CPU (0x%X): P-States not generated !!!\n", gCPUStructure.Family);

diff --git a/rEFIt_UEFI/Platform/cpu.cpp b/rEFIt_UEFI/Platform/cpu.cpp
@@ -336,12 +336,19 @@ void GetCPUProperties (void)
       case CPU_MODEL_ALDERLAKE_ULT:
       case CPU_MODEL_RAPTORLAKE_B:
       case CPU_MODEL_METEORLAKE:
-      case CPU_MODEL_ARROWLAKE:
         msr = AsmReadMsr64(MSR_CORE_THREAD_COUNT);  //0x35
         DBG("MSR 0x35    %16llX\n", msr);
         gCPUStructure.Cores   = (UINT8)bitfield((UINT32)msr, 31, 16);
         gCPUStructure.Threads = (UINT8)bitfield((UINT32)msr, 15,  0);
         break;
+      case CPU_MODEL_ARROWLAKE:
+      case CPU_MODEL_ARROWLAKE_X:
+      case CPU_MODEL_ARROWLAKE_U:
+        msr = AsmReadMsr64(MSR_CORE_THREAD_COUNT);  //0x35
+        DBG("MSR 0x35    %16llX\n", msr);
+        gCPUStructure.Cores   = (UINT8)bitfield((UINT32)msr, 31, 16);
+        gCPUStructure.Threads = gCPUStructure.Cores; // no hyperthreading
+        break;
 
       case CPU_MODEL_DALES:
       case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core
@@ -421,7 +428,7 @@ void GetCPUProperties (void)
     gCPUStructure.Threads = 4;
   }
 
-  //New for SkyLake 0x4E, 0x5E
+  //New for SkyLake 0x4E, 0x5E and up
   if(gCPUStructure.CPUID[CPUID_0][EAX] >= 0x15) {
     UINT32 Num, Denom;
     DoCpuid(0x15, gCPUStructure.CPUID[CPUID_15]);
@@ -540,6 +547,8 @@ void GetCPUProperties (void)
            case CPU_MODEL_RAPTORLAKE:
            case CPU_MODEL_METEORLAKE:
            case CPU_MODEL_ARROWLAKE:
+           case CPU_MODEL_ARROWLAKE_X:
+           case CPU_MODEL_ARROWLAKE_U:
 
             gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz
              gCPUStructure.CPUFrequency = gCPUStructure.TSCFrequency;
@@ -1428,6 +1437,8 @@ UINT16 GetAdvancedCpuType()
           case CPU_MODEL_RAPTORLAKE:
           case CPU_MODEL_METEORLAKE:
           case CPU_MODEL_ARROWLAKE:
+          case CPU_MODEL_ARROWLAKE_X:
+          case CPU_MODEL_ARROWLAKE_U:
             if ( gCPUStructure.BrandString.contains("Core(TM) i3") )
               return 0x905; // Core i3 - Apple doesn't use it
             if ( gCPUStructure.BrandString.contains("Core(TM) i5-1") )
@@ -1566,6 +1577,8 @@ MacModel GetDefaultModel()
       case CPU_MODEL_ICELAKE_A:
       case CPU_MODEL_ICELAKE_C:
       case CPU_MODEL_ICELAKE_D:
+      case CPU_MODEL_ALDERLAKE_ULT:  //???
+      case CPU_MODEL_ARROWLAKE_U:
         DefaultType = MacBookPro161;
         break;
      default:
@@ -1678,13 +1691,15 @@ MacModel GetDefaultModel()
         DefaultType = MacPro61;
         break;
       case CPU_MODEL_ALDERLAKE:
-      case CPU_MODEL_ALDERLAKE_ULT:  //???
+
       case CPU_MODEL_RAPTORLAKE_B:
       case CPU_MODEL_COMETLAKE_S:
       case CPU_MODEL_ROCKETLAKE:
       case CPU_MODEL_RAPTORLAKE:
       case CPU_MODEL_METEORLAKE:
       case CPU_MODEL_ARROWLAKE:
+      case CPU_MODEL_ARROWLAKE_X:
+
         DefaultType = MacPro71;
         break;
       default:

diff --git a/rEFIt_UEFI/Platform/cpu.h b/rEFIt_UEFI/Platform/cpu.h
@@ -83,6 +83,8 @@
 #define CPU_MODEL_RAPTORLAKE    0xB7  /* 13h Raptor Lake */
 #define CPU_MODEL_RAPTORLAKE_B  0xBF  /* 13h Raptor Lake, i5-13400h */
 #define CPU_MODEL_ARROWLAKE		0xC6
+#define CPU_MODEL_ARROWLAKE_X	0xC5  /* 15h Arrow Lake */
+#define CPU_MODEL_ARROWLAKE_U	0xB5  /* 15h Arrow Lake */
 
 #define CPU_VENDOR_INTEL        0x756E6547
 #define CPU_VENDOR_AMD          0x68747541
+2 −0		Include/Acidanthera/Library/OcCpuLib.h
+2 −0		Include/Intel/IndustryStandard/ProcessorInfo.h
+2 −0		Library/OcCpuLib/AppleCpuSupport.c
+12 −2		Library/OcCpuLib/OcCpuLib.c