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new cpu 12th, 13th
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Signed-off-by: SergeySlice <[email protected]>
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@SergeySlice
SergeySlice committed Dec 11, 2023
1 parent bd45a8c commit 2325f37
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Showing 4 changed files with 38 additions and 18 deletions.
16 changes: 9 additions & 7 deletions Include/IndustryStandard/ProcessorInfo.h
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Expand Up @@ -195,13 +195,15 @@ enum {
#define CPU_MODEL_COMETLAKE_Y 0xA5 /* aka 10th generation Amber Lake Y */
#define CPU_MODEL_COMETLAKE_U 0xA6
//From Clover collection
#define CPU_MODEL_ATOM_TM 0x86 /* Tremont */
#define CPU_MODEL_TIGERLAKE_C 0x8C /* 11h generation Tiger Lake */
#define CPU_MODEL_TIGERLAKE_D 0x8D /* 11h generation Tiger Lake */
#define CPU_MODEL_ALDERLAKE 0x97 /* 12h generation Alder Lake */
#define CPU_MODEL_ROCKETLAKE 0xA7 /* 11h Rocket Lake */
#define CPU_MODEL_RAPTORLAKE 0xB7 /* 13h Raptor Lake */
#define CPU_MODEL_METEORLAKE 0xAA /* 14h Meteor Lake */
#define CPU_MODEL_ATOM_TM 0x86 /* Tremont */
#define CPU_MODEL_TIGERLAKE_C 0x8C /* 11h generation Tiger Lake */
#define CPU_MODEL_TIGERLAKE_D 0x8D /* 11h generation Tiger Lake */
#define CPU_MODEL_ALDERLAKE 0x97 /* 12h generation Alder Lake */
#define CPU_MODEL_ALDERLAKE_ULT 0x9A /* 12h generation Alder Lake, i5-12500h */
#define CPU_MODEL_ROCKETLAKE 0xA7 /* 11h Rocket Lake */
#define CPU_MODEL_RAPTORLAKE 0xB7 /* 13h Raptor Lake */
#define CPU_MODEL_RAPTORLAKE_B 0xBF /* 13h Raptor Lake, i5-13400h */
#define CPU_MODEL_METEORLAKE 0xAA /* 14h Meteor Lake */

#define CPU_SOCKET_UNKNOWN 0x02
#define CPU_SOCKET_PGA478 0x0F
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6 changes: 5 additions & 1 deletion rEFIt_UEFI/Platform/StateGenerator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -275,8 +275,10 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
case CPU_MODEL_COMETLAKE_U:
case CPU_MODEL_TIGERLAKE_C:
case CPU_MODEL_TIGERLAKE_D:
case CPU_MODEL_ALDERLAKE:
case CPU_MODEL_ROCKETLAKE:
case CPU_MODEL_ALDERLAKE:
case CPU_MODEL_ALDERLAKE_ULT:
case CPU_MODEL_RAPTORLAKE_B:
case CPU_MODEL_RAPTORLAKE:
case CPU_MODEL_METEORLAKE:
{
Expand Down Expand Up @@ -350,6 +352,8 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
(gCPUStructure.Model == CPU_MODEL_ROCKETLAKE) ||
(gCPUStructure.Model == CPU_MODEL_ALDERLAKE) ||
(gCPUStructure.Model == CPU_MODEL_RAPTORLAKE) ||
(gCPUStructure.Model == CPU_MODEL_ALDERLAKE_ULT) ||
(gCPUStructure.Model == CPU_MODEL_RAPTORLAKE_B) ||
(gCPUStructure.Model == CPU_MODEL_METEORLAKE) ||
(gCPUStructure.Model == CPU_MODEL_COMETLAKE_S) ||
(gCPUStructure.Model == CPU_MODEL_COMETLAKE_Y) ||
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29 changes: 20 additions & 9 deletions rEFIt_UEFI/Platform/cpu.cpp
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Expand Up @@ -326,9 +326,11 @@ void GetCPUProperties (void)
case CPU_MODEL_COMETLAKE_U:
case CPU_MODEL_TIGERLAKE_C:
case CPU_MODEL_TIGERLAKE_D:
case CPU_MODEL_ALDERLAKE:
case CPU_MODEL_ROCKETLAKE:
case CPU_MODEL_ALDERLAKE:
case CPU_MODEL_RAPTORLAKE:
case CPU_MODEL_ALDERLAKE_ULT:
case CPU_MODEL_RAPTORLAKE_B:
case CPU_MODEL_METEORLAKE:
msr = AsmReadMsr64(MSR_CORE_THREAD_COUNT); //0x35
DBG("MSR 0x35 %16llX\n", msr);
Expand Down Expand Up @@ -525,19 +527,22 @@ void GetCPUProperties (void)
case CPU_MODEL_TIGERLAKE_D:
case CPU_MODEL_ALDERLAKE:
case CPU_MODEL_ROCKETLAKE:
case CPU_MODEL_ALDERLAKE_ULT:
case CPU_MODEL_RAPTORLAKE_B:
case CPU_MODEL_RAPTORLAKE:
case CPU_MODEL_METEORLAKE:

gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz
gCPUStructure.CPUFrequency = gCPUStructure.TSCFrequency;


//----test C3 patch
msr = AsmReadMsr64(MSR_PKG_CST_CONFIG_CONTROL); //0xE2
MsgLog("MSR 0xE2 before patch %08llX\n", msr);
if (msr & 0x8000) {
MsgLog("MSR 0xE2 is locked, PM patches will be turned on\n");
GlobalConfig.NeedPMfix = true;
if (gCPUStructure.Model < 0x90) {
//----test C3 patch
msr = AsmReadMsr64(MSR_PKG_CST_CONFIG_CONTROL); //0xE2
MsgLog("MSR 0xE2 before patch %08llX\n", msr);
if (msr & 0x8000) {
MsgLog("MSR 0xE2 is locked, PM patches will be turned on\n");
GlobalConfig.NeedPMfix = true;
}
}
// AsmWriteMsr64(MSR_PKG_CST_CONFIG_CONTROL, (msr & 0x8000000ULL));
// msr = AsmReadMsr64(MSR_PKG_CST_CONFIG_CONTROL);
Expand All @@ -556,7 +561,8 @@ void GetCPUProperties (void)
MsgLog(" EIST is locked and %s\n", (msr & _Bit(16))?"enabled":"disabled");
}

if (gCPUStructure.Model != CPU_MODEL_GOLDMONT && gCPUStructure.Model != CPU_MODEL_AIRMONT &&
if (gCPUStructure.Model != CPU_MODEL_GOLDMONT &&
gCPUStructure.Model != CPU_MODEL_AIRMONT &&
gCPUStructure.Model != CPU_MODEL_AVOTON) {
msr = AsmReadMsr64(MSR_FLEX_RATIO); //0x194
if ((RShiftU64(msr, 16) & 0x01) != 0) {
Expand Down Expand Up @@ -1405,6 +1411,8 @@ UINT16 GetAdvancedCpuType()
case CPU_MODEL_TIGERLAKE_C:
case CPU_MODEL_TIGERLAKE_D:
case CPU_MODEL_ALDERLAKE:
case CPU_MODEL_ALDERLAKE_ULT:
case CPU_MODEL_RAPTORLAKE_B:
case CPU_MODEL_ROCKETLAKE:
case CPU_MODEL_RAPTORLAKE:
case CPU_MODEL_METEORLAKE:
Expand Down Expand Up @@ -1656,7 +1664,10 @@ MacModel GetDefaultModel()
DefaultType = MacPro61;
break;
case CPU_MODEL_ALDERLAKE:
case CPU_MODEL_ALDERLAKE_ULT: //???
case CPU_MODEL_RAPTORLAKE_B:
case CPU_MODEL_COMETLAKE_S:
case CPU_MODEL_ROCKETLAKE:
case CPU_MODEL_RAPTORLAKE:
case CPU_MODEL_METEORLAKE:
DefaultType = MacPro71;
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5 changes: 4 additions & 1 deletion rEFIt_UEFI/Platform/cpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -72,14 +72,17 @@
#define CPU_MODEL_TIGERLAKE_D 0x8D /* 11h generation Tiger Lake */
#define CPU_MODEL_KABYLAKE1 0x8E /* 7h Kabylake Mobile */
#define CPU_MODEL_ALDERLAKE 0x97 /* 12h generation Alder Lake */
#define CPU_MODEL_ALDERLAKE_ULT 0x9A /* 12h generation Alder Lake, i5-12500h */
#define CPU_MODEL_KABYLAKE2 0x9E /* 7h CoffeeLake */
#undef CPU_MODEL_COMETLAKE_S // Jief : mistake in ProcessorInfo.h ?
#define CPU_MODEL_COMETLAKE_S 0x9F /* desktop Comet Lake */
#define CPU_MODEL_COMETLAKE_Y 0xA5 /* 10h Comet Lake */
#define CPU_MODEL_COMETLAKE_U 0xA6 /* 10h Comet Lake */
#define CPU_MODEL_ROCKETLAKE 0xA7 /* 11h Rocket Lake */
#define CPU_MODEL_METEORLAKE 0xAA /* 14h Meteor Lake */
#define CPU_MODEL_RAPTORLAKE 0xB7 /* 13h Raptor Lake */
#define CPU_MODEL_METEORLAKE 0xAA
#define CPU_MODEL_RAPTORLAKE_B 0xBF /* 13h Raptor Lake, i5-13400h */


#define CPU_VENDOR_INTEL 0x756E6547
#define CPU_VENDOR_AMD 0x68747541
Expand Down

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