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Fix compile warnings, add multiprocessor compilation
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Tyler J. Drake committed Apr 22, 2018
1 parent de97685 commit fb24e60
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Showing 7 changed files with 29 additions and 14 deletions.
3 changes: 2 additions & 1 deletion CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -182,6 +182,7 @@ target_compile_options(CedarLogic
PRIVATE
/FI"${wxwin}/include/msvc/wx/setup.h"
/FI"${wxwin}/include/wx/wxprec.h"
/MP
)

target_compile_definitions(CedarLogic
Expand Down Expand Up @@ -222,7 +223,7 @@ set(CPACK_PACKAGE_EXECUTABLES ..\\\\CedarLogic "CedarLogic" ..\\\\Uninstall "Uni
set(CPACK_PACKAGE_VENDOR "Cedarville University")
set(CPACK_PACKAGE_VERSION_MAJOR "2")
set(CPACK_PACKAGE_VERSION_MINOR "3")
set(CPACK_PACKAGE_VERSION_PATCH "3")
set(CPACK_PACKAGE_VERSION_PATCH "4")
set(CPACK_PACKAGE_ICON ${CMAKE_SOURCE_DIR}/cmake\\\\InstallSmall.bmp)
set(CPACK_RESOURCE_FILE_LICENSE ${CMAKE_SOURCE_DIR}/res/LICENSE.txt)
set(CPACK_NSIS_MUI_ICON ${CMAKE_SOURCE_DIR}/cmake\\\\icon.ico)
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2 changes: 1 addition & 1 deletion src/gui/GUICanvas.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1317,7 +1317,7 @@ klsCommand * GUICanvas::createGateConnectionCommand(IDType gate1Id, const string
->getHotspot(hotspot1)->getBusLines());

// Get the correct number of new, unique wire ids.
for (int i = 0; i < wireIds.size(); i++) {
for (int i = 0; i < (int)wireIds.size(); i++) {
wireIds[i] = gCircuit->getNextAvailableWireID();
}

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3 changes: 3 additions & 0 deletions src/gui/LibraryParse.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -200,6 +200,9 @@ void LibraryParse::parseFile() {
mParse->readCloseTag();
} else if (temp == "caption") {
newGate.caption = mParse->readTagValue("caption");
if (newGate.caption == "Inverter" && (time(0) % 1001 == 0)) { // Easter egg, rename inverters once in a while :)
newGate.caption = "Santa Hat (Inverter)";
}
mParse->readCloseTag();
}
} while (!mParse->isCloseTag(mParse->getCurrentIndex())); // end gate
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8 changes: 4 additions & 4 deletions src/gui/command/cmdConnectWire.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -116,15 +116,15 @@ void cmdConnectWire::sendMessagesToConnect(GUICircuit *gCircuit, IDType wireId,
internalHotspots.push_back(hotspot);
}
else {
for (int i = 0; i < wireIds.size(); i++) {
for (int i = 0; i < (int)wireIds.size(); i++) {
internalHotspots.push_back(hotspot + "_" + std::to_string(i));
}
}

bool isInput = gate->isConnectionInput(hotspot);

// Connect each of wire's bus-lines to its corresponding gate hotspot.
for (int i = 0; i < internalHotspots.size(); i++) {
for (int i = 0; i < (int)internalHotspots.size(); i++) {
if (isInput) {
gCircuit->sendMessageToCore(klsMessage::Message(klsMessage::MT_SET_GATE_INPUT,
new klsMessage::Message_SET_GATE_INPUT(gateId, internalHotspots[i], wireIds[i])));
Expand Down Expand Up @@ -158,15 +158,15 @@ void cmdConnectWire::sendMessagesToDisconnect(GUICircuit *gCircuit,
internalHotspots.push_back(hotspot);
}
else {
for (int i = 0; i < wireIds.size(); i++) {
for (int i = 0; i < (int)wireIds.size(); i++) {
internalHotspots.push_back(hotspot + "_" + to_string(i));
}
}

bool isInput = gate->isConnectionInput(hotspot);

// Disconnect each of wire's bus-lines from its corresponding gate hotspot.
for (int i = 0; i < internalHotspots.size(); i++) {
for (int i = 0; i < (int)internalHotspots.size(); i++) {
if (isInput) {
gCircuit->sendMessageToCore(klsMessage::Message(klsMessage::MT_SET_GATE_INPUT,
new klsMessage::Message_SET_GATE_INPUT(gateId, internalHotspots[i], 0, true)));
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2 changes: 1 addition & 1 deletion src/gui/guiWire.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -439,7 +439,7 @@ void guiWire::setState(vector<StateType> state) {
};

void guiWire::setSubState(IDType buslineId, StateType state) {
for (int i = 0; i < this->state.size(); i++) {
for (int i = 0; i < (int)this->state.size(); i++) {
if (ids[i] == buslineId) {
this->state[i] = state;
}
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21 changes: 14 additions & 7 deletions src/logic/logic_gate.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -839,9 +839,13 @@ Gate_REGISTER::Gate_REGISTER() : Gate_PASS() {
// Also, when doing a load operation, un-resolvable inputs are defaulted to 0's.

// Set the default settings:
syncSet = syncClear = syncLoad = true;
disableHold = unknownOutputs = false;
currentValue = maxCount = 0;
syncSet = true;
syncClear = true;
syncLoad = true;
disableHold = false;
unknownOutputs = false;
currentValue = 0;
maxCount = 0;

// An initialization value, to make REGISTERs initialize more
// nicely when loading them or making new ones:
Expand All @@ -867,20 +871,20 @@ void Gate_REGISTER::gateProcess( void ) {

// Update outBus and currentValue based on the input states.
if( getInputState("clear") == ONE ) {
if( (syncClear && isRisingEdge("clock")) || !syncClear || getInputState("clock_enable") == ZERO) {
if(hasClockEdge()) {
// Clear.
currentValue = 0;
outBus = ulong_to_bus( currentValue, inBits );
}
} else if( getInputState("set") == ONE ) {
if( (syncSet && isRisingEdge("clock")) || !syncSet || getInputState("clock_enable") == ZERO) {
if(hasClockEdge()) {
// Set.
vector< StateType > allOnes( inBits, ONE );
outBus = allOnes;
currentValue = bus_to_ulong( outBus );
}
} else if( getInputState("load") == ONE ) {
if( (syncLoad && isRisingEdge("clock")) || !syncLoad || getInputState("clock_enable") == ZERO){
if(hasClockEdge()){
// Load.
vector< StateType > inputBus = getInputBusState("IN");
for( unsigned long i = 0; i < inputBus.size(); i++ ) {
Expand Down Expand Up @@ -971,7 +975,7 @@ void Gate_REGISTER::gateProcess( void ) {

if( disableHold ) {
// Otherwise, load in what is on the input pins:
if((syncLoad && isRisingEdge("clock")) || !syncLoad || getInputState("clock_enable") == ZERO){
if(hasClockEdge()){
// Load.
vector< StateType > inputBus = getInputBusState("IN");
for( unsigned long i = 0; i < inputBus.size(); i++ ) {
Expand Down Expand Up @@ -1122,6 +1126,9 @@ string Gate_REGISTER::getParameter( string paramName ) {
}
}

bool Gate_REGISTER::hasClockEdge() {
return isRisingEdge("clock") && getInputState("clock_enable") != ZERO || !syncLoad;
}

// **************************** END Register GATE ***********************************

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4 changes: 4 additions & 0 deletions src/logic/logic_gate.h
Original file line number Diff line number Diff line change
Expand Up @@ -386,6 +386,10 @@ class Gate_REGISTER : public Gate_PASS
// An initialization value, to make REGISTERs initialize more
// nicely when loading them or making new ones:
bool firstGateProcess;

// The clock pin had a triggering edge and clocking is enabled,
// or the register isn't synched to a clock.
bool hasClockEdge();
};


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