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  • Xidian University
  • 15:01 (UTC +08:00)

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Carl7yan/README.md

Hi there 👋

About Me

  • Hi, I'm Shengjie, a digital IC verification engineer with 2 years internship and 0.5 year work experience.
  • I‘m passionate about using GitHub to collaborate with others and giving back to the community.

Contact Me

Popular repositories Loading

  1. hello-world hello-world Public archive

    Hi, I'm Carl. Nice to meet you guys! @_@

    1

  2. apb-uart-uvm-env apb-uart-uvm-env Public

    Forked from Lampro-Mellon/apb-uart-uvm-env

    SystemVerilog 1

  3. Carl7yan Carl7yan Public

  4. Viterbi-Decoder-in-Verilog Viterbi-Decoder-in-Verilog Public

    Forked from jfoshea/Viterbi-Decoder-in-Verilog

    An efficient implementation of the Viterbi decoding algorithm in Verilog

    Verilog

  5. sv_uvm_start sv_uvm_start Public

    SystemVerilog