This repository contains Verilog implementations of fundamental digital logic design components. Each module is designed to perform specific operations, such as addition, multiplexing, or arithmetic logic unit (ALU) computations. These modules are useful for constructing and simulating complex digital systems.
- Half Adder
- Full Adder
- Multiplexers
- 4x1 Multiplexer
- 2x1 Multiplexer
- 2-bit 2x1 Multiplexer
- 16-bit 2x1 Multiplexer
- 16-bit 4x1 Multiplexer
- Arithmetic Logic Unit (ALU)
- 16-bit ALU
- 1-bit ALU
- 1-bit ALU (Significant Bit)
- Register File
- 16-bit Register
- Decoder
Module Name: halfadder
A combinational circuit that adds two 1-bit binary numbers. It outputs a sum (S) and carry (C).
- Inputs:
x,y - Outputs:
S,C
Module Name: fulladder
Adds three 1-bit binary numbers (two inputs and a carry-in). It outputs a sum (S) and carry-out (C).
- Inputs:
x,y,z - Outputs:
S,C
Module Name: mux4x1
A 4-to-1 multiplexer selects one of the four inputs based on a 2-bit select line.
- Inputs:
i0,i1,i2,i3,select - Output:
y
Module Name: mux2x1
A 2-to-1 multiplexer selects one of two inputs based on a single-bit select line.
- Inputs:
A,B,select - Output:
OUT
Module Name: mux2bit2x1
A multiplexer that selects between two 2-bit inputs.
- Inputs:
A,B,select - Output:
OUT
Module Name: mux16bit2x1
A multiplexer that selects between two 16-bit inputs.
- Inputs:
A,B,select - Output:
OUT
Module Name: mux4x1_16bit
A multiplexer that selects one of four 16-bit inputs based on a 2-bit select line.
- Inputs:
i0,i1,i2,i3,select - Output:
y
Module Name: ALU
A 16-bit ALU capable of performing various arithmetic and logical operations based on a 4-bit opcode.
- Inputs:
a,b,op - Outputs:
result,zero
Module Name: ALU1
Performs arithmetic and logical operations on single-bit inputs with configurable control signals.
- Inputs:
a,b,ainvert,binvert,op,less,carryin - Outputs:
carryout,result
Module Name: ALUmsb
Handles the most significant bit in multi-bit ALU operations, with support for carry and result propagation.
- Inputs:
a,b,ainvert,binvert,op,less,carryin - Outputs:
carryout,result,sum
Module Name: reg_file
A register file with three 16-bit registers, supporting read and write operations.
- Inputs:
rr1,rr2,wr,wd,regwrite,clock - Outputs:
rd1,rd2
Module Name: register
A 16-bit register that stores input data (WriteData) on the clock signal (CLK).
- Inputs:
WriteData,CLK - Outputs:
ReadData
Module Name: decoder
A 2-to-4 decoder used to enable specific outputs based on a 2-bit input.
To use these modules:
- Include the required module files in your Verilog project.
- Instantiate the modules as needed in your top-level design or testbench.
- Simulate using a Verilog simulator such as ModelSim or Vivado.
This repository is open source and licensed under the MIT License.