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Add test for routines RTEDDG UCDG
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jinningwang committed Nov 24, 2024
1 parent 8c2d342 commit a214e21
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Showing 2 changed files with 93 additions and 7 deletions.
17 changes: 10 additions & 7 deletions tests/test_rtn_rted.py
Original file line number Diff line number Diff line change
Expand Up @@ -12,11 +12,9 @@ class TestRTED(unittest.TestCase):

def setUp(self) -> None:
self.ss = ams.load(ams.get_case("5bus/pjm5bus_demo.xlsx"),
setup=True,
default_config=True,
no_output=True,
)
self.ss.RTED.run(solver='CLARABEL')
setup=True, default_config=True, no_output=True)
# decrease load first
self.ss.PQ.set(src='p0', attr='v', idx=['PQ_1', 'PQ_2'], value=[0.3, 0.3])

def test_init(self):
"""
Expand Down Expand Up @@ -83,6 +81,7 @@ def test_dc2ac(self):
"""
Test `RTED.dc2ac()` method.
"""
self.ss.RTED.run(solver='CLARABEL')
self.ss.RTED.dc2ac()
self.assertTrue(self.ss.RTED.converted, "AC conversion failed!")
self.assertTrue(self.ss.RTED.exec_time > 0, "Execution time is not greater than 0.")
Expand Down Expand Up @@ -110,7 +109,8 @@ class TestRTEDDG(unittest.TestCase):
def setUp(self) -> None:
self.ss = ams.load(ams.get_case("5bus/pjm5bus_demo.xlsx"),
setup=True, default_config=True, no_output=True)
self.ss.RTEDDG.run(solver='CLARABEL')
# decrease load first
self.ss.PQ.set(src='p0', attr='v', idx=['PQ_1', 'PQ_2'], value=[0.3, 0.3])

def test_init(self):
"""
Expand Down Expand Up @@ -177,6 +177,7 @@ def test_dc2ac(self):
"""
Test `RTEDDG.dc2ac()` method.
"""
self.ss.RTEDDG.run(solver='CLARABEL')
self.ss.RTEDDG.dc2ac()
self.assertTrue(self.ss.RTEDDG.converted, "AC conversion failed!")
self.assertTrue(self.ss.RTEDDG.exec_time > 0, "Execution time is not greater than 0.")
Expand Down Expand Up @@ -204,6 +205,8 @@ class TestRTEDES(unittest.TestCase):
def setUp(self) -> None:
self.ss = ams.load(ams.get_case("5bus/pjm5bus_uced_esd1.xlsx"),
setup=True, default_config=True, no_output=True)
# decrease load first
self.ss.PQ.set(src='p0', attr='v', idx=['PQ_1', 'PQ_2'], value=[0.3, 0.3])

def test_init(self):
"""
Expand Down Expand Up @@ -254,7 +257,7 @@ def test_set_load(self):
pgs = self.ss.RTEDES.pg.v.sum()

# --- set load ---
self.ss.PQ.set(src='p0', attr='v', idx='PQ_1', value=1)
self.ss.PQ.set(src='p0', attr='v', idx='PQ_1', value=0.05)
self.ss.RTEDES.update()

self.ss.RTEDES.run(solver='SCIP')
Expand Down
83 changes: 83 additions & 0 deletions tests/test_rtn_uc.py
Original file line number Diff line number Diff line change
Expand Up @@ -86,6 +86,87 @@ def test_trip_line(self):
self.ss.Line.alter(src='u', idx='Line_3', value=1)


class TestUCDG(unittest.TestCase):
"""
Test routine `UCDG`.
"""

def setUp(self) -> None:
self.ss = ams.load(ams.get_case("5bus/pjm5bus_demo.xlsx"),
setup=True, default_config=True, no_output=True)
# decrease load first
self.ss.PQ.set(src='p0', attr='v', idx=['PQ_1', 'PQ_2'], value=[0.3, 0.3])
# run `_initial_guess()`
self.off_gen = self.ss.UCDG._initial_guess()

def test_initial_guess(self):
"""
Test initial guess.
"""
u_off_gen = self.ss.StaticGen.get(src='u', idx=self.off_gen)
np.testing.assert_equal(u_off_gen, np.zeros_like(u_off_gen),
err_msg="UCDG._initial_guess() failed!")

def test_init(self):
"""
Test initialization.
"""
self.ss.UCDG.init()
self.assertTrue(self.ss.UCDG.initialized, "UCDG initialization failed!")

@skip_unittest_without_MIP
def test_trip_gen(self):
"""
Test generator tripping.
"""
self.ss.UCDG.run(solver='SCIP')
self.assertTrue(self.ss.UCDG.converged, "UCDG did not converge!")
pg_off_gen = self.ss.UCDG.get(src='pg', attr='v', idx=self.off_gen)
np.testing.assert_almost_equal(np.zeros_like(pg_off_gen),
pg_off_gen, decimal=6,
err_msg="Off generators are not turned off!")

@skip_unittest_without_MIP
def test_set_load(self):
"""
Test setting and tripping load.
"""
self.ss.UCDG.run(solver='SCIP')
pgs = self.ss.UCDG.pg.v.sum()

# --- set load ---
self.ss.PQ.set(src='p0', attr='v', idx='PQ_1', value=0.1)
self.ss.UCDG.update()

self.ss.UCDG.run(solver='SCIP')
pgs_pqt = self.ss.UCDG.pg.v.sum()
self.assertLess(pgs_pqt, pgs, "Load set does not take effect!")

# --- trip load ---
self.ss.PQ.alter(src='u', idx='PQ_2', value=0)
self.ss.UCDG.update()

self.ss.UCDG.run(solver='SCIP')
pgs_pqt2 = self.ss.UCDG.pg.v.sum()
self.assertLess(pgs_pqt2, pgs_pqt, "Load trip does not take effect!")

@skip_unittest_without_MIP
def test_trip_line(self):
"""
Test line tripping.
"""
self.ss.Line.set(src='u', attr='v', idx='Line_3', value=0)
self.ss.UCDG.update()

self.ss.UCDG.run(solver='SCIP')
self.assertTrue(self.ss.UCDG.converged, "UCDG did not converge under line trip!")
plf_l3 = self.ss.UCDG.get(src='plf', attr='v', idx='Line_3')
np.testing.assert_almost_equal(np.zeros_like(plf_l3),
plf_l3, decimal=6)

self.ss.Line.alter(src='u', idx='Line_3', value=1)


class TestUCES(unittest.TestCase):
"""
Test routine `UCES`.
Expand All @@ -94,6 +175,8 @@ class TestUCES(unittest.TestCase):
def setUp(self) -> None:
self.ss = ams.load(ams.get_case("5bus/pjm5bus_uced_esd1.xlsx"),
setup=True, default_config=True, no_output=True)
# decrease load first
self.ss.PQ.set(src='p0', attr='v', idx=['PQ_1', 'PQ_2'], value=[0.3, 0.3])
# run `_initial_guess()`
self.off_gen = self.ss.UCES._initial_guess()

Expand Down

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