fixed DDR4 timing bug? #110
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Apologies if this has already been addressed in #47 but the source still seems incorrect. Lines 291-294 seem redundant / incompatible with lines 295-298 and wr-wr timings for sibling banks seem to be missing.
If this is not a mistake, could you please explain how these timings correspond to the JEDEC standards or any DDR4 catalog from Micron, etc. (page number, timing name in the standard)?
Thank you!
Helena