Update math_test example with 48-bit math (#520)

The individual commits by @runer112 were: 817a526 Test 48-bit math routines 973bb53 Fix printing 43ee410 Test operations even if not hooked up to routines yet eab2d36 Try to coax compiler into using 24-bit and 48-bit math routines 059b8aa Use bit-precise integer types when available 422e489 Fix UB from casting e83d384 Remove unnecessary coments a4e66c6 Update test expected values
CE-Programming · Nov 18, 2024 · c79fe8d · c79fe8d
1 parent a7980d2
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Showing 2 changed files with 263 additions and 151 deletions.
diff --git a/examples/standalone_examples/math_test/autotest.json b/examples/standalone_examples/math_test/autotest.json
@@ -62,167 +62,167 @@
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "0B3D9374"
+        "B9510AD8"
       ]
     },
     "neg": {
       "description": "neg",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "10A84E1B"
+        "7122851F"
       ]
     },
     "abs": {
       "description": "abs",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "D7807035"
+        "7614EAC3"
       ]
     },
     "bitrev": {
       "description": "bitrev",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "BBADF82E"
+        "1492AAC4"
       ]
     },
     "bswap": {
       "description": "bswap",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "7709B5AE"
+        "C9C416BB"
       ]
     },
     "popcnt": {
       "description": "popcnt",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "62628040"
+        "E3E46F91"
       ]
     },
     "and": {
       "description": "and",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "32DEF9D5"
+        "844F62ED"
       ]
     },
     "or": {
       "description": "or",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "4E247920"
+        "6529AA0B"
       ]
     },
     "xor": {
       "description": "xor",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "257F7002"
+        "2CAD0372"
       ]
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     "add": {
       "description": "add",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "CD575A4D"
+        "F94DD5D6"
       ]
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     "sub": {
       "description": "sub",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "EE1C5453"
+        "167FF1A7"
       ]
     },
     "shl": {
       "description": "shl",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "FD8CA2EC"
+        "BF87D382"
       ]
     },
     "shru": {
       "description": "shru",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "9754CB4F"
+        "0F7AE868"
       ]
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     "shrs": {
       "description": "shrs",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "AB5BE5CB"
+        "A0BA88A7"
       ]
     },
     "mulu": {
       "description": "mulu",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "C6A6FF7D"
+        "B7CBA439"
       ]
     },
     "divu": {
       "description": "divu",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "F973C020"
+        "1AC569AB"
       ]
     },
     "remu": {
       "description": "remu",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "5196C205"
+        "D29F5374"
       ]
     },
     "divs": {
       "description": "divs",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "2A13A348"
+        "63331417"
       ]
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     "rems": {
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       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "F45969EF"
+        "1322808B"
       ]
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     "div_q": {
       "description": "div_q",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "EAFFC6D3"
+        "B5F9B54D"
       ]
     },
     "div_r": {
       "description": "div_r",
       "start": "vram_start",
       "size": "vram_16_size",
       "expected_CRCs": [
-        "B9786654"
+        "60B1E228"
       ]
     },
     "done": {