added commit interfce to cvxif

Makefile

@@ -218,7 +218,8 @@ src :=  core/include/$(target)_config_pkg.sv
         corev_apu/tb/rvfi_tracer.sv                                                  \
         corev_apu/tb/common/uart.sv                                                  \
         corev_apu/tb/common/SimDTM.sv                                                \
-        corev_apu/tb/common/SimJTAG.sv
+        corev_apu/tb/common/SimJTAG.sv												 \
+		core/cvxif_example/cvxif_registers.sv
 
 src := $(addprefix $(root-dir), $(src))
 
@@ -317,11 +318,11 @@ build: $(library) $(library)/.build-srcs $(library)/.build-tb
 
 # src files
 $(library)/.build-srcs: $(library)
-	$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors -f core/Flist.cva6 $(list_incdir) -suppress 2583 +defines+$(defines)
-	$(VLOG) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583 +defines+$(defines)
+	$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors -f core/Flist.cva6 $(list_incdir) -suppress 2583 -suppress 13389 +defines+$(defines)
+	$(VLOG) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583 -suppress 13389 +defines+$(defines)
 	# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
-	$(VCOM) $(compile_flag_vhd) -work $(library) $(filter %.vhd,$(uart_src)) +defines+$(defines)
-	$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(tbs) $(list_incdir) -suppress 2583 +defines+$(defines)
+	$(VCOM) $(compile_flag_vhd) -work $(library) -suppress 13389 $(filter %.vhd,$(uart_src)) +defines+$(defines)
+	$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(tbs) $(list_incdir) -suppress 2583 -suppress 13389 +defines+$(defines)
 	touch $(library)/.build-srcs
 
 # build TBs

core/cva6.sv

@@ -134,7 +134,10 @@ module cva6
     input cvxif_resp_t cvxif_resp_i,
     // memory side
     output noc_req_t noc_req_o,
-    input noc_resp_t noc_resp_i
+    input noc_resp_t noc_resp_i,
+    // to CV-X-IF
+    output logic                commit_ack_to_cvxif,
+    output scoreboard_entry_t   commit_sbe_to_cvxif
 );
 
   // ------------------------------------------
@@ -644,6 +647,10 @@ module cva6
       .*
   );
 
+  // Assign commit signals (to cvxif)
+  assign commit_ack_to_cvxif = commit_ack;
+  assign commit_sbe_to_cvxif = commit_instr_id_commit;
+
   // ---------
   // EX
   // ---------

core/cvxif_example/cvxif_example_coprocessor.sv

@@ -12,11 +12,14 @@
 module cvxif_example_coprocessor
   import cvxif_pkg::*;
   import cvxif_instr_pkg::*;
+  import ariane_pkg::*;
 (
-    input  logic        clk_i,        // Clock
-    input  logic        rst_ni,       // Asynchronous reset active low
-    input  cvxif_req_t  cvxif_req_i,
-    output cvxif_resp_t cvxif_resp_o
+    input  logic                clk_i,        // Clock
+    input  logic                rst_ni,       // Asynchronous reset active low
+    input  cvxif_req_t          cvxif_req_i,
+    output cvxif_resp_t         cvxif_resp_o,
+    input  logic                commit_ack_i, // commit_ack from commit stage
+    input  scoreboard_entry_t   commit_sbe_i  // from scoreboard 
 );
 
   //Compressed interface

core/cvxif_example/cvxif_registers.sv

@@ -0,0 +1,49 @@
+// By Hugo BABIN-RIBY for CVA6 2023 hackathon
+// Desc : cvxif non-addressed registers
+
+module cvxif_registers #(
+    parameter Nb_of_regs = 150,
+    parameter signed_regs = 0,
+    parameter reg_width = 9
+) (
+    // CVA6 base signals
+    input logic clk_i,
+    input logic rst_ni,
+    // Dump signal, equivalent to reset, set all to 0
+    input logic dump_i,
+    // WriteEnable signal
+    input logic we_i,
+    // actual data to load
+    input logic [reg_width-1:0] wb_data_i,
+    // register memory
+    output logic [Nb_of_regs-1:0][reg_width-1:0] regs_q
+);
+
+logic [reg_width-1:0] wb_pointer_q; // todo : fix this, supposed to be log_2(150)
+
+// overflowing ?
+logic overflow;
+assign overflow = (wb_pointer_q >= Nb_of_regs);
+
+if(signed_regs) begin
+    logic signed   [Nb_of_regs-1:0][reg_width-1:0] regs_q;
+end else begin
+    logic unsigned [Nb_of_regs-1:0][reg_width-1:0] regs_q;
+end
+
+integer i;
+always_ff @(posedge clk_i) begin
+    //hadle reset signals (nrst_i & dump_i)
+    if (~rst_ni || dump_i) begin
+        for (i = 0; i < Nb_of_regs; i++) begin : reset_cvxif_regs
+            regs_q[i] <= 9'b0;
+        end
+        wb_pointer_q <= 0;
+    end
+    if(we_i) begin
+        regs_q[wb_pointer_q] <= wb_data_i;
+        wb_pointer_q <= wb_pointer_q + 1;
+    end 
+end
+
+endmodule

core/decoder.sv

@@ -811,10 +811,10 @@ module decoder
             3'b101: instruction_o.op = ariane_pkg::LHU;
             3'b110:
             if (riscv::XLEN == 64) instruction_o.op = ariane_pkg::LWU;
-            else illegal_instr = 1'b1;
+            else instruction_o.op = ariane_pkg::LBC;
             3'b011:
             if (riscv::XLEN == 64) instruction_o.op = ariane_pkg::LD;
-            else illegal_instr = 1'b1;
+            else instruction_o.op = ariane_pkg::LBCU;
             default: illegal_instr = 1'b1;
           endcase
         end

core/include/ariane_pkg.sv

@@ -414,6 +414,9 @@ package ariane_pkg;
     LB,
     SB,
     LBU,
+    // Load Byte Cvxif
+    LBC,
+    LBCU,
     // Atomic Memory Operations
     AMO_LRW,
     AMO_LRD,
@@ -1005,7 +1008,8 @@ package ariane_pkg;
         return 2'b10;
       end
       LH, LHU, SH, FLH, FSH: return 2'b01;
-      LB, LBU, SB, FLB, FSB: return 2'b00;
+      // Added BEs for LBC & LBCU
+      LB, LBU, SB, FLB, FSB, LBC, LBCU: return 2'b00;
       default:               return 2'b11;
     endcase
   endfunction

core/load_unit.sv

@@ -452,7 +452,8 @@ module load_unit
 
 
   // prepare these signals for faster selection in the next cycle
-  assign rdata_is_signed    =   ldbuf_rdata.operation inside {ariane_pkg::LW,  ariane_pkg::LH,  ariane_pkg::LB};
+  // Added LBC as signed
+  assign rdata_is_signed    =   ldbuf_rdata.operation inside {ariane_pkg::LW,  ariane_pkg::LH,  ariane_pkg::LB, ariane_pkg::LBC};
   assign rdata_is_fp_signed =   ldbuf_rdata.operation inside {ariane_pkg::FLW, ariane_pkg::FLH, ariane_pkg::FLB};
   assign rdata_offset       = ((ldbuf_rdata.operation inside {ariane_pkg::LW,  ariane_pkg::FLW}) & riscv::IS_XLEN64) ? ldbuf_rdata.address_offset + 3 :
                                 ( ldbuf_rdata.operation inside {ariane_pkg::LH,  ariane_pkg::FLH})                     ? ldbuf_rdata.address_offset + 1 :
@@ -474,7 +475,8 @@ module load_unit
       result_o = {{riscv::XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]};
       ariane_pkg::LH, ariane_pkg::LHU:
       result_o = {{riscv::XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]};
-      ariane_pkg::LB, ariane_pkg::LBU:
+      // Added LBC and LBCU in result MUX
+      ariane_pkg::LB, ariane_pkg::LBU, ariane_pkg::LBC, ariane_pkg::LBCU:
       result_o = {{riscv::XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]};
       ariane_pkg::FLW: begin
         if (CVA6Cfg.FpPresent) begin

sw/app/hugo_test/main.c

@@ -0,0 +1,38 @@
+#include <stdint.h>
+#include "uart.h"
+
+int main(void)
+{
+        char a = -10;
+        char* a_addr = &a;
+
+        for(char i = 0; i < 150; i++){
+                asm volatile("lbc x0 0(%0)"
+                : 
+                : "r" (a_addr)
+                );
+                asm volatile("lbcu x0 0(%0)"
+                : 
+                : "r" (a_addr)
+                );
+                asm volatile("lb x0 0(%0)"
+                : 
+                : "r" (a_addr)
+                );
+                asm volatile("lbu x0 0(%0)"
+                : 
+                : "r" (a_addr)
+                );
+        }
+
+        uint8_t message[12] = "Hello World";
+        UART_init(&g_uart_0,
+                UART_115200_BAUD,
+                UART_DATA_8_BITS | UART_NO_PARITY | UART_ONE_STOP_BIT);
+
+        UART_polled_tx_string(&g_uart_0, message);
+
+        while(UART_tx_complete(&g_uart_0)==0);
+
+        return(0);
+}

sw/app/mnist/NetworkPropagate.c

@@ -34,8 +34,67 @@ static void macsOnRange(const UDATA_T* __restrict inputs,
                         int nb_iterations)
 {
     for (int iter = 0; iter < nb_iterations; ++iter) {
+        /*
+        asm volatile ("mul %0, %1, %2"
+            : "=r" (transitionValue)
+            : "r" (inputs[iter]), "r" (weights[iter]));
+
+        asm volatile ("add %0, %1, %2"
+            : "=r" (*weightedSum)
+            : "r" (*weightedSum), "r" (transitionValue));
+        */
+
+        asm volatile ("lbc x0, 0(%0)"
+                        :
+                        : "r" (weightedSum)); 
+
+        asm volatile ("lbcu x0, 0(%0)"
+                        :
+                        : "r" (weightedSum)); 
+
+        asm volatile ("lb x0, 0(%0)"
+                        :
+                        : "r" (weightedSum));
+
+        asm volatile ("lbcu x0, 0(%0)"
+                        :
+                        : "r" (weightedSum)); 
+
+        asm volatile ("lb x0, 0(%0)"
+                        :
+                        : "r" (*weightedSum)); 
+
+        asm volatile ("lbu x0, 0(%0)"
+                        :
+                        : "r" (weightedSum)); 
+
         *weightedSum += inputs[iter] * weights[iter];
+
+        asm volatile ("lb x0, 0(%0)"
+                        :
+                        : "r" (weightedSum)); 
+
+        asm volatile ("lb x0, 0(%0)"
+                        :
+                        : "r" (weightedSum)); 
+
+        asm volatile ("lbu x0, 0(%0)"
+                        :
+                        : "r" (weightedSum)); 
+
     }
+    asm volatile ("lbcu x0, 0(%0)"
+                        :
+                        : "r" (weightedSum)); 
+
+        asm volatile ("lb x0, 0(%0)"
+                        :
+                        : "r" (weightedSum)); 
+
+        asm volatile ("lbu x0, 0(%0)"
+                        :
+                        : "r" (weightedSum));
+
 }
 
 static UDATA_T saturate(SUM_T value, uint32_t sat) {