diff --git a/Data/instructions.json b/Data/instructions.json
index 69c5738..d9534bd 100644
--- a/Data/instructions.json
+++ b/Data/instructions.json
@@ -8662,6 +8662,7 @@
         "width32": 8,
         "width64": 16,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -8716,6 +8717,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -8771,6 +8773,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -8826,6 +8829,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -8876,6 +8880,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -8933,6 +8938,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -8990,6 +8996,7 @@
         "width32": 8,
         "width64": 16,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66020,6 +66027,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66057,6 +66065,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66094,6 +66103,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66131,6 +66141,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66165,6 +66176,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66200,6 +66212,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66235,6 +66248,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66270,6 +66284,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66305,6 +66320,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66340,6 +66356,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66375,6 +66392,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66410,6 +66428,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66450,6 +66469,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66489,6 +66509,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66528,6 +66549,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66572,6 +66594,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66608,6 +66631,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66644,6 +66668,7 @@
         "width32": 4,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66718,6 +66743,7 @@
         "width16": 16,
         "width32": 32,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66791,6 +66817,7 @@
         "width16": 16,
         "width32": 32,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66825,6 +66852,7 @@
         "width32": 2,
         "width64": 2,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66880,6 +66908,7 @@
         "width32": 2,
         "width64": 2,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66935,6 +66964,7 @@
         "width32": 4,
         "width64": 4,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -66990,6 +67020,7 @@
         "width32": 8,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
@@ -67045,6 +67076,7 @@
         "width32": 8,
         "width64": 8,
         "visible": false,
+        "implictdisp": true,
         "ignore_seg_override": true
       }
     ],
diff --git a/Zydis/Generator/Zydis.Generator.Tables.pas b/Zydis/Generator/Zydis.Generator.Tables.pas
index 10ef7db..ba6dfc2 100644
--- a/Zydis/Generator/Zydis.Generator.Tables.pas
+++ b/Zydis/Generator/Zydis.Generator.Tables.pas
@@ -814,8 +814,9 @@ class procedure TZYOperandTableGenerator.Generate(Generator: TZYBaseGenerator;
           begin
             { op  } Writer.StructBegin;
             { mem } Writer.StructBegin('mem');
-                    { seg         } Writer.WriteDec(Ord(Item.MemorySegment));
-                    { base        } Writer.WriteStr('ZYDIS_IMPLMEM_BASE_' +
+                    { implicitdisp  } Writer.WriteDec(Ord(Item.HasImplictDisp));
+                    { seg           } Writer.WriteDec(Ord(Item.MemorySegment));
+                    { base          } Writer.WriteStr('ZYDIS_IMPLMEM_BASE_' +
                                       TZYBaseRegister.ZydisStrings[Item.MemoryBase]);
             { op  } Writer.StructEnd;
             { mem } Writer.StructEnd;
diff --git a/Zydis/Zydis.Enums.pas b/Zydis/Zydis.Enums.pas
index 0c96fbf..119f339 100644
--- a/Zydis/Zydis.Enums.pas
+++ b/Zydis/Zydis.Enums.pas
@@ -238,7 +238,7 @@   TZYEnumRegister = record
       // Misc registers
       'mxcsr',      'pkru',       'xcr0',       'gdtr',
       'ldtr',       'idtr',       'tr',         'bndcfg',
-      'bndstatus',  'uif' ,       'ia32_kernel_gsbase'
+      'bndstatus',  'uif' ,       'ia32_kernel_gs_base'
     );
   end;
   TZYRegister = TZYEnumRegister.Enum;
diff --git a/Zydis/Zydis.InstructionEditor.pas b/Zydis/Zydis.InstructionEditor.pas
index 5bde4b6..f1f737c 100644
--- a/Zydis/Zydis.InstructionEditor.pas
+++ b/Zydis/Zydis.InstructionEditor.pas
@@ -386,6 +386,7 @@   TZYInstructionOperand = class sealed(TZYLinkedJSONOPersistent<TZYInstructionOp
     FScaleFactor: TZYScaleFactor;
     FWidth: array[1..3] of TZYSemanticOperandWidth;
     FVisible: Boolean;
+    FHasImplictDisp : Boolean;
     FIsMultisource4: Boolean;
     FIgnoreSegmentOverride: Boolean;
   strict private
@@ -402,6 +403,7 @@   TZYInstructionOperand = class sealed(TZYLinkedJSONOPersistent<TZYInstructionOp
     procedure SetScaleFactor(const Value: TZYScaleFactor); inline;
     procedure SetWidth(Index: Integer; const Value: TZYSemanticOperandWidth); inline;
     procedure SetVisible(const Value: Boolean); inline;
+    procedure SetHasImplictDisp(const Value: Boolean); inline;
     procedure SetIsMultisource4(const Value: Boolean); inline;
     procedure SetIgnoreSegmentOverride(const Value: Boolean); inline;
   protected
@@ -432,6 +434,7 @@   TZYInstructionOperand = class sealed(TZYLinkedJSONOPersistent<TZYInstructionOp
     property Width32: TZYSemanticOperandWidth index 2 read GetWidth write SetWidth default 0;
     property Width64: TZYSemanticOperandWidth index 3 read GetWidth write SetWidth default 0;
     property Visible: Boolean read FVisible write SetVisible default true;
+    property HasImplictDisp: Boolean read FHasImplictDisp write SetHasImplictDisp default true;
     property Visibility: TZYOperandVisibility read GetVisibility;
     property IsMultisource4: Boolean read FIsMultisource4 write SetIsMultisource4 default false;
     property IgnoreSegmentOverride: Boolean read FIgnoreSegmentOverride write SetIgnoreSegmentOverride default false;
@@ -2013,6 +2016,7 @@ procedure TZYInstructionOperand.AssignTo(Dest: TPersistent);
         D.SetWidth(I, FWidth[I]);
       end;
       D.SetVisible(FVisible);
+      D.SetHasImplictDisp(FHasImplictDisp);
       D.SetIsMultisource4(FIsMultisource4);
       D.SetIgnoreSegmentOverride(FIgnoreSegmentOverride);
     finally
@@ -2123,6 +2127,7 @@ procedure TZYInstructionOperand.LoadFromJSON(const JSON: IJSONObjectReader);
     SetWidth(2, JSON.ReadInteger('width32', 0));
     SetWidth(3, JSON.ReadInteger('width64', 0));
     SetVisible(JSON.ReadBoolean('visible', true));
+    SetHasImplictDisp(JSON.ReadBoolean('implictdisp', false));
     SetIsMultisource4(JSON.ReadBoolean('is_multisource4', false));
     SetIgnoreSegmentOverride(JSON.ReadBoolean('ignore_seg_override', false));
   finally
@@ -2325,6 +2330,15 @@ procedure TZYInstructionOperand.SetVisible(const Value: Boolean);
   end;
 end;
 
+procedure TZYInstructionOperand.SetHasImplictDisp(const Value: Boolean);
+begin
+  if (FHasImplictDisp <> Value) then
+  begin
+    FHasImplictDisp := Value;
+    Update;
+  end;
+end;
+
 procedure TZYInstructionOperand.SetWidth(Index: Integer; const Value: TZYSemanticOperandWidth);
 begin
   if (FWidth[Index] <> Value) then