From edf16e07daf5bf644afb7bc0111e8ddb9ff32ffe Mon Sep 17 00:00:00 2001 From: zifeihan Date: Tue, 30 Jul 2024 16:40:24 +0800 Subject: [PATCH] Polishing --- src/hotspot/cpu/riscv/vm_version_riscv.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/hotspot/cpu/riscv/vm_version_riscv.cpp b/src/hotspot/cpu/riscv/vm_version_riscv.cpp index 0c4045ff533a6..ac2d6cde1a227 100644 --- a/src/hotspot/cpu/riscv/vm_version_riscv.cpp +++ b/src/hotspot/cpu/riscv/vm_version_riscv.cpp @@ -261,6 +261,10 @@ void VM_Version::c2_initialize() { } } + // NOTE: Make sure codes dependent on UseRVV are put after MaxVectorSize initialize, + // as there are extra checks inside it which could disable UseRVV + // in some situations. + if (FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) { FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true); } @@ -328,10 +332,6 @@ void VM_Version::c2_initialize() { FLAG_SET_DEFAULT(UseMD5Intrinsics, true); } - // NOTE: Make sure codes dependent on UseRVV are put after MaxVectorSize initialize, - // as there are extra checks inside it which could disable UseRVV - // in some situations. - // Adler32 if (UseRVV) { if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {