cpu_decode_unofficial.h

// *** WARNING ***
// This file is generated by gen6502.rb
// Keep untouched or ruin the abstraction
// generated file
#pragma once
#include "cpu.h"
#include "cpu_decode.h"
#include "utils.h"

// [STP] OP:02 Mode:IMPLIED Length:1 Memory:-
// Semantics:NOTIMPL
static inline void cpu_decode_unofficial_02_stp(cpu_t *self)
{
    // NOTIMPL(T)
    WARN("STP[02] not implemented\n");
}

// [SLO] OP:03 Mode:PRE_INDIRECT_X Length:2 Memory:RMW
// Semantics:T(R), C(T & 0x80), W, T(T << 1), W, T(A | T), N, Z, A
static inline void cpu_decode_unofficial_03_slo(cpu_t *self, uint16_t addr)
{
    uint16_t tmp;
    // T(R)
    tmp = cpu_read(self, addr);
    // C(T & 0x80)
    self->reg.carry = (bool)(tmp & 0x80);
    // W(T)
    cpu_write(self, addr, tmp);
    // T(T << 1)
    tmp = tmp << 1;
    // W(T)
    cpu_write(self, addr, tmp);
    // T(A | T)
    tmp = self->reg.a | tmp;
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
    // A(T)
    self->reg.a = tmp;
}

// [ANC] OP:0B Mode:IMMEDIATE Length:2 Memory:-
// Semantics:T(A & T), N, Z, A, C(N)
static inline void cpu_decode_unofficial_0B_anc(cpu_t *self, uint8_t value)
{
    uint16_t tmp = value;
    // T(A & T)
    tmp = self->reg.a & tmp;
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
    // A(T)
    self->reg.a = tmp;
    // C(N)
    self->reg.carry = (bool)(self->reg.negative);
}

// [RLA] OP:23 Mode:PRE_INDIRECT_X Length:2 Memory:RMW
// Semantics:T(R), W, T((T << 1) | C), C(T & 0x100), W, T(A & T), N, Z, A
static inline void cpu_decode_unofficial_23_rla(cpu_t *self, uint16_t addr)
{
    uint16_t tmp;
    // T(R)
    tmp = cpu_read(self, addr);
    // W(T)
    cpu_write(self, addr, tmp);
    // T((T << 1) | C)
    tmp = (tmp << 1) | self->reg.carry;
    // C(T & 0x100)
    self->reg.carry = (bool)(tmp & 0x100);
    // W(T)
    cpu_write(self, addr, tmp);
    // T(A & T)
    tmp = self->reg.a & tmp;
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
    // A(T)
    self->reg.a = tmp;
}

// [SRE] OP:43 Mode:PRE_INDIRECT_X Length:2 Memory:RMW
// Semantics:T(R), W, C(T & 0x01), T(T >> 1), W, T(A ^ T), N, Z, A
static inline void cpu_decode_unofficial_43_sre(cpu_t *self, uint16_t addr)
{
    uint16_t tmp;
    // T(R)
    tmp = cpu_read(self, addr);
    // W(T)
    cpu_write(self, addr, tmp);
    // C(T & 0x01)
    self->reg.carry = (bool)(tmp & 0x01);
    // T(T >> 1)
    tmp = tmp >> 1;
    // W(T)
    cpu_write(self, addr, tmp);
    // T(A ^ T)
    tmp = self->reg.a ^ tmp;
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
    // A(T)
    self->reg.a = tmp;
}

// [ALR] OP:4B Mode:IMMEDIATE Length:2 Memory:-
// Semantics:T(A & T), C(T & 0x01), T(T >> 1), N, Z, A
static inline void cpu_decode_unofficial_4B_alr(cpu_t *self, uint8_t value)
{
    uint16_t tmp = value;
    // T(A & T)
    tmp = self->reg.a & tmp;
    // C(T & 0x01)
    self->reg.carry = (bool)(tmp & 0x01);
    // T(T >> 1)
    tmp = tmp >> 1;
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
    // A(T)
    self->reg.a = tmp;
}

// [RRA] OP:63 Mode:PRE_INDIRECT_X Length:2 Memory:RMW
// Semantics:T(R), W, T(T | (C ? 0x100 : 0)), C(T & 0x01), T(T >> 1), W, M(T), T(T + A + C), N(T & 0x80), Z, C(T > 0xff), V((A ^ M ^ 0x80) & (A ^ T) & 0x80), A
static inline void cpu_decode_unofficial_63_rra(cpu_t *self, uint16_t addr)
{
    uint16_t tmp;
    // T(R)
    tmp = cpu_read(self, addr);
    // W(T)
    cpu_write(self, addr, tmp);
    // T(T | (C ? 0x100 : 0))
    tmp = tmp | (self->reg.carry ? 0x100 : 0);
    // C(T & 0x01)
    self->reg.carry = (bool)(tmp & 0x01);
    // T(T >> 1)
    tmp = tmp >> 1;
    // W(T)
    cpu_write(self, addr, tmp);
    // M(T)
    addr = tmp;
    // T(T + A + C)
    tmp = tmp + self->reg.a + self->reg.carry;
    // N(T & 0x80)
    self->reg.negative = ((tmp & 0x80) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
    // C(T > 0xff)
    self->reg.carry = (bool)(tmp > 0xff);
    // V((A ^ M ^ 0x80) & (A ^ T) & 0x80)
    self->reg.overflow = (bool)((self->reg.a ^ addr ^ 0x80) & (self->reg.a ^ tmp) & 0x80);
    // A(T)
    self->reg.a = tmp;
}

// [ARR] OP:6B Mode:IMMEDIATE Length:2 Memory:-
// Semantics:T(A & T), T(T | (C ? 0x100 : 0)), T(T >> 1), C(T & 0x40), V(((T >> 6) ^ (T >> 5)) & 1), N, Z, A
static inline void cpu_decode_unofficial_6B_arr(cpu_t *self, uint8_t value)
{
    uint16_t tmp = value;
    // T(A & T)
    tmp = self->reg.a & tmp;
    // T(T | (C ? 0x100 : 0))
    tmp = tmp | (self->reg.carry ? 0x100 : 0);
    // T(T >> 1)
    tmp = tmp >> 1;
    // C(T & 0x40)
    self->reg.carry = (bool)(tmp & 0x40);
    // V(((T >> 6) ^ (T >> 5)) & 1)
    self->reg.overflow = (bool)(((tmp >> 6) ^ (tmp >> 5)) & 1);
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
    // A(T)
    self->reg.a = tmp;
}

// [SAX] OP:83 Mode:PRE_INDIRECT_X Length:2 Memory:W
// Semantics:W(A & X)
static inline void cpu_decode_unofficial_83_sax(cpu_t *self, uint16_t addr)
{
    // W(A & X)
    cpu_write(self, addr, self->reg.a & self->reg.x);
}

// [XAA] OP:8B Mode:IMMEDIATE Length:2 Memory:-
// Semantics:UNUSED(T), NOTIMPL
static inline void cpu_decode_unofficial_8B_xaa(cpu_t *self, uint8_t value)
{
    uint16_t tmp = value;
    // UNUSED(T)
    (void)(tmp);
    // NOTIMPL(T)
    WARN("XAA[8B] not implemented\n");
}

// [AHX] OP:93 Mode:POST_INDIRECT_Y Length:2 Memory:R
// Semantics:UNUSED(T), NOTIMPL
static inline void cpu_decode_unofficial_93_ahx(cpu_t *self, uint8_t value)
{
    uint16_t tmp = value;
    // UNUSED(T)
    (void)(tmp);
    // NOTIMPL(T)
    WARN("AHX[93] not implemented\n");
}

// [TAS] OP:9B Mode:ABSOLUTE_Y Length:3 Memory:R
// Semantics:UNUSED(T), NOTIMPL
static inline void cpu_decode_unofficial_9B_tas(cpu_t *self, uint8_t value)
{
    uint16_t tmp = value;
    // UNUSED(T)
    (void)(tmp);
    // NOTIMPL(T)
    WARN("TAS[9B] not implemented\n");
}

// [SHY] OP:9C Mode:ABSOLUTE_X Length:3 Memory:RMW
// Semantics:T(Y & ((((M - X) >> 8) + 1) & 0xff)), M((((M - X) >> 8) == (M >> 8)) ? M : ((T << 8) | (M & 0xff))), W
static inline void cpu_decode_unofficial_9C_shy(cpu_t *self, uint16_t addr)
{
    uint16_t tmp;
    // T(Y & ((((M - X) >> 8) + 1) & 0xff))
    tmp = self->reg.y & ((((addr - self->reg.x) >> 8) + 1) & 0xff);
    // M((((M - X) >> 8) == (M >> 8)) ? M : ((T << 8) | (M & 0xff)))
    addr = (((addr - self->reg.x) >> 8) == (addr >> 8)) ? addr : ((tmp << 8) | (addr & 0xff));
    // W(T)
    cpu_write(self, addr, tmp);
}

// [SHX] OP:9E Mode:ABSOLUTE_Y Length:3 Memory:RMW
// Semantics:T(X & ((((M - Y) >> 8) + 1) & 0xff)), M((((M - Y) >> 8) == (M >> 8)) ? M : ((T << 8) | (M & 0xff))), W
static inline void cpu_decode_unofficial_9E_shx(cpu_t *self, uint16_t addr)
{
    uint16_t tmp;
    // T(X & ((((M - Y) >> 8) + 1) & 0xff))
    tmp = self->reg.x & ((((addr - self->reg.y) >> 8) + 1) & 0xff);
    // M((((M - Y) >> 8) == (M >> 8)) ? M : ((T << 8) | (M & 0xff)))
    addr = (((addr - self->reg.y) >> 8) == (addr >> 8)) ? addr : ((tmp << 8) | (addr & 0xff));
    // W(T)
    cpu_write(self, addr, tmp);
}

// [LAX] OP:A3 Mode:PRE_INDIRECT_X Length:2 Memory:R
// Semantics:A, X, N, Z
static inline void cpu_decode_unofficial_A3_lax(cpu_t *self, uint8_t value)
{
    uint16_t tmp = value;
    // A(T)
    self->reg.a = tmp;
    // X(T)
    self->reg.x = tmp;
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
}

// [LAS] OP:BB Mode:ABSOLUTE_Y Length:3 Memory:R
// Semantics:UNUSED(T), NOTIMPL
static inline void cpu_decode_unofficial_BB_las(cpu_t *self, uint8_t value)
{
    uint16_t tmp = value;
    // UNUSED(T)
    (void)(tmp);
    // NOTIMPL(T)
    WARN("LAS[BB] not implemented\n");
}

// [DCP] OP:C3 Mode:PRE_INDIRECT_X Length:2 Memory:RMW
// Semantics:T(R), W, T((T - 1) & 0xff), W, T(A - T), C(T < 0x100), N, Z
static inline void cpu_decode_unofficial_C3_dcp(cpu_t *self, uint16_t addr)
{
    uint16_t tmp;
    // T(R)
    tmp = cpu_read(self, addr);
    // W(T)
    cpu_write(self, addr, tmp);
    // T((T - 1) & 0xff)
    tmp = (tmp - 1) & 0xff;
    // W(T)
    cpu_write(self, addr, tmp);
    // T(A - T)
    tmp = self->reg.a - tmp;
    // C(T < 0x100)
    self->reg.carry = (bool)(tmp < 0x100);
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
}

// [AXS] OP:CB Mode:IMMEDIATE Length:2 Memory:-
// Semantics:T((A & X) - T), C(T < 0x100), N, Z, X
static inline void cpu_decode_unofficial_CB_axs(cpu_t *self, uint8_t value)
{
    uint16_t tmp = value;
    // T((A & X) - T)
    tmp = (self->reg.a & self->reg.x) - tmp;
    // C(T < 0x100)
    self->reg.carry = (bool)(tmp < 0x100);
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
    // X(T)
    self->reg.x = tmp;
}

// [ISC] OP:E3 Mode:PRE_INDIRECT_X Length:2 Memory:RMW
// Semantics:T(R), W, T((T + 1) & 0xff), W, M(T), T(A - T - (C ? 0 : 1)), N, Z, V((A ^ T) & (A ^ M) & 0x80), C(T < 0x100), A
static inline void cpu_decode_unofficial_E3_isc(cpu_t *self, uint16_t addr)
{
    uint16_t tmp;
    // T(R)
    tmp = cpu_read(self, addr);
    // W(T)
    cpu_write(self, addr, tmp);
    // T((T + 1) & 0xff)
    tmp = (tmp + 1) & 0xff;
    // W(T)
    cpu_write(self, addr, tmp);
    // M(T)
    addr = tmp;
    // T(A - T - (C ? 0 : 1))
    tmp = self->reg.a - tmp - (self->reg.carry ? 0 : 1);
    // N(T)
    self->reg.negative = ((tmp) >> 7) & 1;
    // Z(T)
    self->reg.zero = !((tmp) & 0xff);
    // V((A ^ T) & (A ^ M) & 0x80)
    self->reg.overflow = (bool)((self->reg.a ^ tmp) & (self->reg.a ^ addr) & 0x80);
    // C(T < 0x100)
    self->reg.carry = (bool)(tmp < 0x100);
    // A(T)
    self->reg.a = tmp;
}