From f5f9270a42d1ef25a486af9e3ab8119f956f4283 Mon Sep 17 00:00:00 2001
From: I <1091761+wx257osn2@users.noreply.github.com>
Date: Tue, 2 Apr 2024 20:08:25 +0900
Subject: [PATCH] use Advanced SIMD only on 64bit ARM

---
 include/qoixx.hpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/qoixx.hpp b/include/qoixx.hpp
index 8f17fbe..ea24d3e 100644
--- a/include/qoixx.hpp
+++ b/include/qoixx.hpp
@@ -17,7 +17,7 @@
 #if defined(__ARM_FEATURE_SVE)
 #include<arm_sve.h>
 #include<arm_neon.h>
-#elif defined(__ARM_NEON)
+#elif defined(__aarch64__)
 #include<arm_neon.h>
 #elif defined(__AVX2__)
 #include<immintrin.h>
@@ -589,7 +589,7 @@ class qoi{
 
     push<sizeof(padding)>(p_, padding);
   }
-#elif defined(__ARM_NEON)
+#elif defined(__aarch64__)
   template<bool Alpha>
   using pixels_type = std::conditional_t<Alpha, uint8x16x4_t, uint8x16x3_t>;
   template<bool Alpha>
@@ -1155,7 +1155,7 @@ class qoi{
       const auto b1 = p.pull();
       --size;
 
-#if defined(__ARM_NEON) and not defined(QOIXX_NO_SIMD)
+#if defined(__aarch64__) and not defined(QOIXX_NO_SIMD)
 #define QOIXX_HPP_DECODE_RUN(px, run) { \
     if constexpr(Pusher::is_contiguous){ \
       ++run; \
@@ -1335,7 +1335,7 @@ class qoi{
 #undef QOIXX_HPP_SVE_REGISTER_SIZE_SWITCH_CASE
 #undef QOIXX_HPP_SVE_REGISTER_SIZE_SWITCH
     else
-#elif defined(__ARM_NEON)
+#elif defined(__aarch64__)
     if constexpr(coT::pusher::is_contiguous && coU::puller::is_contiguous)
       if(desc.channels == 4)
         encode_neon<4>(p, puller, desc);