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hello_world_out.txt
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hello_world_out.txt
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DEBUG:root:
Tick: 0
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: PUSH 2
PC MPC AR BR TOS
16 1 16 0 0
DS: []
RS: []
DEBUG:root:
Tick: 1
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
16 3 16 0 0
DS: []
RS: []
DEBUG:root:
Tick: 2
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
17 4 16 0 0
DS: [0]
RS: []
DEBUG:root:
Tick: 3
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
17 5 17 0 0
DS: [0]
RS: []
DEBUG:root:
Tick: 4
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
18 0 17 0 2
DS: [0]
RS: []
DEBUG:root:
Tick: 5
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: LOAD
PC MPC AR BR TOS
18 1 18 0 2
DS: [0]
RS: []
DEBUG:root:
Tick: 6
MicroInstruction: LATCH_AR, SEL_AR_TOS, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
18 32 18 0 2
DS: [0]
RS: []
DEBUG:root:
Tick: 7
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
18 33 2 0 2
DS: [0]
RS: []
DEBUG:root:
Tick: 8
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
19 0 2 0 13
DS: [0]
RS: []
DEBUG:root:
Tick: 9
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: DUP
PC MPC AR BR TOS
19 1 19 0 13
DS: [0]
RS: []
DEBUG:root:
Tick: 10
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
19 12 19 0 13
DS: [0]
RS: []
DEBUG:root:
Tick: 11
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
20 0 19 0 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 12
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: PUSH 1
PC MPC AR BR TOS
20 1 20 0 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 13
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
20 3 20 0 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 14
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
21 4 20 0 13
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 15
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
21 5 21 0 13
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 16
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
22 0 21 0 1
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 17
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: LOAD
PC MPC AR BR TOS
22 1 22 0 1
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 18
MicroInstruction: LATCH_AR, SEL_AR_TOS, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
22 32 22 0 1
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 19
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
22 33 1 0 1
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 20
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
23 0 1 0 1
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 21
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: OUT
PC MPC AR BR TOS
23 1 23 0 1
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 22
MicroInstruction: OUT, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
23 40 23 0 1
DS: [0, 13, 13]
RS: []
DEBUG:root:Output: writing 13 on port 1
DEBUG:root:
Tick: 23
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
23 41 23 0 1
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 24
MicroInstruction: LATCH_TOS, SEL_TOS_DS, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
23 42 23 0 1
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 25
MicroInstruction: DS_POP, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
23 43 23 0 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 26
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
24 0 23 0 13
DS: [0]
RS: []
DEBUG:root:
Tick: 27
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: DUP
PC MPC AR BR TOS
24 1 24 0 13
DS: [0]
RS: []
DEBUG:root:
Tick: 28
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
24 12 24 0 13
DS: [0]
RS: []
DEBUG:root:
Tick: 29
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
25 0 24 0 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 30
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: PUSH 49
PC MPC AR BR TOS
25 1 25 0 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 31
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
25 3 25 0 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 32
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
26 4 25 0 13
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 33
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
26 5 26 0 13
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 34
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
27 0 26 0 49
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 35
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: SWAP
PC MPC AR BR TOS
27 1 27 0 49
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 36
MicroInstruction: LATCH_BR, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
27 8 27 0 49
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 37
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
27 9 27 13 49
DS: [0, 13, 13]
RS: []
DEBUG:root:
Tick: 38
MicroInstruction: DS_PUSH, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
27 10 27 13 49
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 39
MicroInstruction: LATCH_TOS, SEL_TOS_BR, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
27 11 27 13 49
DS: [0, 13, 49]
RS: []
DEBUG:root:
Tick: 40
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
28 0 27 13 13
DS: [0, 13, 49]
RS: []
DEBUG:root:
Tick: 41
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: JZ
PC MPC AR BR TOS
28 1 28 13 13
DS: [0, 13, 49]
RS: []
DEBUG:root:
Tick: 42
MicroInstruction: LATCH_PC, SEL_PC_JZ, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
28 47 28 13 13
DS: [0, 13, 49]
RS: []
DEBUG:root:
Tick: 43
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
29 48 28 13 13
DS: [0, 13, 49]
RS: []
DEBUG:root:
Tick: 44
MicroInstruction: LATCH_TOS, SEL_TOS_DS, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
29 49 28 13 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 45
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
29 50 28 13 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 46
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
29 0 28 13 13
DS: [0]
RS: []
DEBUG:root:
Tick: 47
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: PUSH 2
PC MPC AR BR TOS
29 1 29 13 13
DS: [0]
RS: []
DEBUG:root:
Tick: 48
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
29 3 29 13 13
DS: [0]
RS: []
DEBUG:root:
Tick: 49
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
30 4 29 13 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 50
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
30 5 30 13 13
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 51
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
31 0 30 13 2
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 52
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: INC
PC MPC AR BR TOS
31 1 31 13 2
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 53
MicroInstruction: ALU_SUM, ALU_RIGHT_OP_ZERO, ALU_INC, LATCH_TOS, SEL_TOS_ALU, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
31 20 31 13 2
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 54
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
32 0 31 13 3
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 55
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: DUP
PC MPC AR BR TOS
32 1 32 13 3
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 56
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
32 12 32 13 3
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 57
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
33 0 32 13 3
DS: [0, 13, 3]
RS: []
DEBUG:root:
Tick: 58
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: LOAD
PC MPC AR BR TOS
33 1 33 13 3
DS: [0, 13, 3]
RS: []
DEBUG:root:
Tick: 59
MicroInstruction: LATCH_AR, SEL_AR_TOS, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
33 32 33 13 3
DS: [0, 13, 3]
RS: []
DEBUG:root:
Tick: 60
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
33 33 3 13 3
DS: [0, 13, 3]
RS: []
DEBUG:root:
Tick: 61
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
34 0 3 13 72
DS: [0, 13, 3]
RS: []
DEBUG:root:
Tick: 62
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: PUSH 1
PC MPC AR BR TOS
34 1 34 13 72
DS: [0, 13, 3]
RS: []
DEBUG:root:
Tick: 63
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
34 3 34 13 72
DS: [0, 13, 3]
RS: []
DEBUG:root:
Tick: 64
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
35 4 34 13 72
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:
Tick: 65
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
35 5 35 13 72
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:
Tick: 66
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
36 0 35 13 1
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:
Tick: 67
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: LOAD
PC MPC AR BR TOS
36 1 36 13 1
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:
Tick: 68
MicroInstruction: LATCH_AR, SEL_AR_TOS, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
36 32 36 13 1
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:
Tick: 69
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
36 33 1 13 1
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:
Tick: 70
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
37 0 1 13 1
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:
Tick: 71
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: OUT
PC MPC AR BR TOS
37 1 37 13 1
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:
Tick: 72
MicroInstruction: OUT, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
37 40 37 13 1
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:Output: writing `H` (72) on port 1
DEBUG:root:
Tick: 73
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
37 41 37 13 1
DS: [0, 13, 3, 72]
RS: []
DEBUG:root:
Tick: 74
MicroInstruction: LATCH_TOS, SEL_TOS_DS, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
37 42 37 13 1
DS: [0, 13, 3]
RS: []
DEBUG:root:
Tick: 75
MicroInstruction: DS_POP, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
37 43 37 13 3
DS: [0, 13, 3]
RS: []
DEBUG:root:
Tick: 76
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
38 0 37 13 3
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 77
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: SWAP
PC MPC AR BR TOS
38 1 38 13 3
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 78
MicroInstruction: LATCH_BR, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
38 8 38 13 3
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 79
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
38 9 38 13 3
DS: [0, 13]
RS: []
DEBUG:root:
Tick: 80
MicroInstruction: DS_PUSH, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
38 10 38 13 3
DS: [0]
RS: []
DEBUG:root:
Tick: 81
MicroInstruction: LATCH_TOS, SEL_TOS_BR, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
38 11 38 13 3
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 82
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
39 0 38 13 13
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 83
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: DEC
PC MPC AR BR TOS
39 1 39 13 13
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 84
MicroInstruction: ALU_SUM, ALU_RIGHT_OP_ZERO, ALU_DEC, LATCH_TOS, SEL_TOS_ALU, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
39 21 39 13 13
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 85
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
40 0 39 13 12
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 86
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: DUP
PC MPC AR BR TOS
40 1 40 13 12
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 87
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
40 12 40 13 12
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 88
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
41 0 40 13 12
DS: [0, 3, 12]
RS: []
DEBUG:root:
Tick: 89
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: PUSH 49
PC MPC AR BR TOS
41 1 41 13 12
DS: [0, 3, 12]
RS: []
DEBUG:root:
Tick: 90
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
41 3 41 13 12
DS: [0, 3, 12]
RS: []
DEBUG:root:
Tick: 91
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
42 4 41 13 12
DS: [0, 3, 12, 12]
RS: []
DEBUG:root:
Tick: 92
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
42 5 42 13 12
DS: [0, 3, 12, 12]
RS: []
DEBUG:root:
Tick: 93
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
43 0 42 13 49
DS: [0, 3, 12, 12]
RS: []
DEBUG:root:
Tick: 94
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: SWAP
PC MPC AR BR TOS
43 1 43 13 49
DS: [0, 3, 12, 12]
RS: []
DEBUG:root:
Tick: 95
MicroInstruction: LATCH_BR, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
43 8 43 13 49
DS: [0, 3, 12, 12]
RS: []
DEBUG:root:
Tick: 96
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
43 9 43 12 49
DS: [0, 3, 12, 12]
RS: []
DEBUG:root:
Tick: 97
MicroInstruction: DS_PUSH, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
43 10 43 12 49
DS: [0, 3, 12]
RS: []
DEBUG:root:
Tick: 98
MicroInstruction: LATCH_TOS, SEL_TOS_BR, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
43 11 43 12 49
DS: [0, 3, 12, 49]
RS: []
DEBUG:root:
Tick: 99
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
44 0 43 12 12
DS: [0, 3, 12, 49]
RS: []
DEBUG:root:
Tick: 100
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: JZ
PC MPC AR BR TOS
44 1 44 12 12
DS: [0, 3, 12, 49]
RS: []
DEBUG:root:
Tick: 101
MicroInstruction: LATCH_PC, SEL_PC_JZ, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
44 47 44 12 12
DS: [0, 3, 12, 49]
RS: []
DEBUG:root:
Tick: 102
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
45 48 44 12 12
DS: [0, 3, 12, 49]
RS: []
DEBUG:root:
Tick: 103
MicroInstruction: LATCH_TOS, SEL_TOS_DS, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
45 49 44 12 12
DS: [0, 3, 12]
RS: []
DEBUG:root:
Tick: 104
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
45 50 44 12 12
DS: [0, 3, 12]
RS: []
DEBUG:root:
Tick: 105
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
45 0 44 12 12
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 106
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: SWAP
PC MPC AR BR TOS
45 1 45 12 12
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 107
MicroInstruction: LATCH_BR, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
45 8 45 12 12
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 108
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
45 9 45 3 12
DS: [0, 3]
RS: []
DEBUG:root:
Tick: 109
MicroInstruction: DS_PUSH, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
45 10 45 3 12
DS: [0]
RS: []
DEBUG:root:
Tick: 110
MicroInstruction: LATCH_TOS, SEL_TOS_BR, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
45 11 45 3 12
DS: [0, 12]
RS: []
DEBUG:root:
Tick: 111
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
46 0 45 3 3
DS: [0, 12]
RS: []
DEBUG:root:
Tick: 112
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: PUSH 31
PC MPC AR BR TOS
46 1 46 3 3
DS: [0, 12]
RS: []
DEBUG:root:
Tick: 113
MicroInstruction: DS_PUSH, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
46 3 46 3 3
DS: [0, 12]
RS: []
DEBUG:root:
Tick: 114
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
47 4 46 3 3
DS: [0, 12, 3]
RS: []
DEBUG:root:
Tick: 115
MicroInstruction: LATCH_TOS, SEL_TOS_MEMORY, LATCH_PC, SEL_PC_NEXT, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
47 5 47 3 3
DS: [0, 12, 3]
RS: []
DEBUG:root:
Tick: 116
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
48 0 47 3 31
DS: [0, 12, 3]
RS: []
DEBUG:root:
Tick: 117
MicroInstruction: LATCH_MPC, SEL_MPC_OPCODE
Instruction: JMP
PC MPC AR BR TOS
48 1 48 3 31
DS: [0, 12, 3]
RS: []
DEBUG:root:
Tick: 118
MicroInstruction: LATCH_PC, SEL_PC_JMP, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
48 44 48 3 31
DS: [0, 12, 3]
RS: []
DEBUG:root:
Tick: 119
MicroInstruction: LATCH_TOS, SEL_TOS_DS, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS
31 45 48 3 31
DS: [0, 12, 3]
RS: []
DEBUG:root:
Tick: 120
MicroInstruction: DS_POP, LATCH_MPC, SEL_MPC_ZERO
PC MPC AR BR TOS
31 46 48 3 3
DS: [0, 12, 3]
RS: []
DEBUG:root:
Tick: 121
MicroInstruction: LATCH_AR, SEL_AR_PC, LATCH_MPC, SEL_MPC_NEXT
PC MPC AR BR TOS