minor update

hw/rtl/VX_platform.vh

@@ -238,11 +238,11 @@
 `define RESET_RELAY(dst, src) \
     `RESET_RELAY_EX (dst, src, 1, 0)
 
-// size(x): 0 -> 0, 1 -> 1, 2 -> 2, 3 -> 2, 4-> 2
-`define TO_OUT_BUF_SIZE(out_reg)    `MIN(out_reg, 2)
+// size(x): 0 -> 0, 1 -> 1, 2 -> 2, 3 -> 2, 4-> 2, 5 -> 2
+`define TO_OUT_BUF_SIZE(s)    `MIN(s, 2)
 
-// reg(x): 0 -> 0, 1 -> 1, 2 -> 0, 3 -> 1, 4 -> 2
-`define TO_OUT_BUF_REG(out_reg)     ((out_reg & 1) + ((out_reg >> 2) << 1))
+// reg(x): 0 -> 0, 1 -> 1, 2 -> 0, 3 -> 1, 4 -> 2, 5 > 3
+`define TO_OUT_BUF_REG(s)     ((s < 2) ? s : (s - 2))
 
 `define REPEAT(n,f,s)   `_REPEAT_``n(f,s)
 `define _REPEAT_0(f,s)

hw/rtl/libs/VX_elastic_buffer.sv

@@ -103,9 +103,9 @@ module VX_elastic_buffer #(
 
         assign ready_in = ~full;
 
-        VX_elastic_buffer #(
+        VX_pipe_buffer #(
             .DATAW (DATAW),
-            .SIZE  ((OUT_REG == 2) ? 1 : 0)
+            .DEPTH ((OUT_REG > 0) ? (OUT_REG-1) : 0)
         ) out_buf (
             .clk       (clk),
             .reset     (reset),

hw/rtl/libs/VX_pipe_buffer.sv

@@ -1,11 +1,11 @@
 // Copyright 2019-2023
-// 
+//
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-// 
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
-// 
+//
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -24,39 +24,53 @@
 
 `TRACING_OFF
 module VX_pipe_buffer #(
-    parameter DATAW    = 1,
-    parameter PASSTHRU = 0
-) ( 
+    parameter DATAW = 1,
+    parameter DEPTH = 1
+) (
     input  wire             clk,
     input  wire             reset,
     input  wire             valid_in,
-    output wire             ready_in,        
+    output wire             ready_in,
     input  wire [DATAW-1:0] data_in,
     output wire [DATAW-1:0] data_out,
     input  wire             ready_out,
     output wire             valid_out
-); 
-    if (PASSTHRU != 0) begin
+);
+    if (DEPTH == 0) begin
         `UNUSED_VAR (clk)
         `UNUSED_VAR (reset)
         assign ready_in  = ready_out;
-        assign valid_out = valid_in;        
+        assign valid_out = valid_in;
         assign data_out  = data_in;
     end else begin
-        wire stall = valid_out && ~ready_out;
-
-        VX_pipe_register #(
-            .DATAW	(1 + DATAW),
-            .RESETW (1)
-        ) pipe_register (
-            .clk      (clk),
-            .reset    (reset),
-            .enable	  (~stall),
-            .data_in  ({valid_in,  data_in}),
-            .data_out ({valid_out, data_out})
-        );
-
-        assign ready_in = ~stall;
+        wire [DEPTH:0] valid;
+    `IGNORE_UNOPTFLAT_BEGIN
+        wire [DEPTH:0] ready;
+    `IGNORE_UNOPTFLAT_END
+        wire [DEPTH:0][DATAW-1:0] data;
+
+        assign valid[0] = valid_in;
+        assign data[0]  = data_in;
+        assign ready_in = ready[0];
+
+        for (genvar i = 0; i < DEPTH; ++i) begin
+            assign ready[i] = (ready[i+1] || ~valid[i+1]);
+            VX_pipe_register #(
+                .DATAW  (1 + DATAW),
+                .RESETW (1)
+            ) pipe_register (
+                .clk      (clk),
+                .reset    (reset),
+                .enable   (ready[i]),
+                .data_in  ({valid[i], data[i]}),
+                .data_out ({valid[i+1], data[i+1]})
+            );
+        end
+
+        assign valid_out = valid[DEPTH];
+        assign data_out = data[DEPTH];
+        assign ready[DEPTH] = ready_out;
+
     end
 
 endmodule