From 811ceb5dc086fc0041dd13ec7a0afcc37550810e Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 21 Aug 2024 13:00:05 -0700 Subject: [PATCH] minor update --- hw/rtl/libs/VX_priority_encoder.sv | 42 +++++++++++++++--------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/hw/rtl/libs/VX_priority_encoder.sv b/hw/rtl/libs/VX_priority_encoder.sv index f96a07bb7..2138ea457 100644 --- a/hw/rtl/libs/VX_priority_encoder.sv +++ b/hw/rtl/libs/VX_priority_encoder.sv @@ -49,6 +49,27 @@ module VX_priority_encoder #( end else if (MODEL == 1) begin + `IGNORE_UNOPTFLAT_BEGIN + wire [N-1:0] higher_pri_regs; + `IGNORE_UNOPTFLAT_END + + assign higher_pri_regs[0] = 1'b0; + for (genvar i = 1; i < N; ++i) begin + assign higher_pri_regs[i] = higher_pri_regs[i-1] | reversed[i-1]; + end + assign onehot_out[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0]; + + VX_lzc #( + .N (N), + .REVERSE (1) + ) lzc ( + .data_in (reversed), + .data_out (index_out), + .valid_out (valid_out) + ); + + end else if (MODEL == 2) begin + wire [N-1:0] scan_lo; VX_scan #( @@ -70,27 +91,6 @@ module VX_priority_encoder #( assign onehot_out = scan_lo & {(~scan_lo[N-2:0]), 1'b1}; - end else if (MODEL == 2) begin - - `IGNORE_UNOPTFLAT_BEGIN - wire [N-1:0] higher_pri_regs; - `IGNORE_UNOPTFLAT_END - - assign higher_pri_regs[0] = 1'b0; - for (genvar i = 1; i < N; ++i) begin - assign higher_pri_regs[i] = higher_pri_regs[i-1] | reversed[i-1]; - end - assign onehot_out[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0]; - - VX_lzc #( - .N (N), - .REVERSE (1) - ) lzc ( - .data_in (reversed), - .data_out (index_out), - .valid_out (valid_out) - ); - end else if (MODEL == 3) begin assign onehot_out = reversed & -reversed;