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qlcnic_83xx_hw.c
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qlcnic_83xx_hw.c
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/*
* QLogic qlcnic NIC Driver
* Copyright (c) 2009-2013 QLogic Corporation
*
* See LICENSE.qlcnic for copyright and licensing details.
*/
#include <linux/if_vlan.h>
#include <linux/ipv6.h>
#include <linux/ethtool.h>
#include <linux/interrupt.h>
#include <linux/aer.h>
#include "qlcnic.h"
#include "qlcnic_sriov.h"
static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
struct qlcnic_cmd_args *);
static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
pci_channel_state_t);
static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
static void qlcnic_83xx_io_resume(struct pci_dev *);
static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
static int qlcnic_83xx_resume(struct qlcnic_adapter *);
static int qlcnic_83xx_shutdown(struct pci_dev *);
static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
#define RSS_HASHTYPE_IP_TCP 0x3
#define QLC_83XX_FW_MBX_CMD 0
#define QLC_SKIP_INACTIVE_PCI_REGS 7
#define QLC_MAX_LEGACY_FUNC_SUPP 8
/* 83xx Module type */
#define QLC_83XX_MODULE_FIBRE_10GBASE_LRM 0x1 /* 10GBase-LRM */
#define QLC_83XX_MODULE_FIBRE_10GBASE_LR 0x2 /* 10GBase-LR */
#define QLC_83XX_MODULE_FIBRE_10GBASE_SR 0x3 /* 10GBase-SR */
#define QLC_83XX_MODULE_DA_10GE_PASSIVE_CP 0x4 /* 10GE passive
* copper(compliant)
*/
#define QLC_83XX_MODULE_DA_10GE_ACTIVE_CP 0x5 /* 10GE active limiting
* copper(compliant)
*/
#define QLC_83XX_MODULE_DA_10GE_LEGACY_CP 0x6 /* 10GE passive copper
* (legacy, best effort)
*/
#define QLC_83XX_MODULE_FIBRE_1000BASE_SX 0x7 /* 1000Base-SX */
#define QLC_83XX_MODULE_FIBRE_1000BASE_LX 0x8 /* 1000Base-LX */
#define QLC_83XX_MODULE_FIBRE_1000BASE_CX 0x9 /* 1000Base-CX */
#define QLC_83XX_MODULE_TP_1000BASE_T 0xa /* 1000Base-T*/
#define QLC_83XX_MODULE_DA_1GE_PASSIVE_CP 0xb /* 1GE passive copper
* (legacy, best effort)
*/
#define QLC_83XX_MODULE_UNKNOWN 0xf /* Unknown module type */
/* Port types */
#define QLC_83XX_10_CAPABLE BIT_8
#define QLC_83XX_100_CAPABLE BIT_9
#define QLC_83XX_1G_CAPABLE BIT_10
#define QLC_83XX_10G_CAPABLE BIT_11
#define QLC_83XX_AUTONEG_ENABLE BIT_15
static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
{QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
{QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
{QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
{QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
{QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
{QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
{QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
{QLCNIC_CMD_INTRPT_TEST, 22, 12},
{QLCNIC_CMD_SET_MTU, 3, 1},
{QLCNIC_CMD_READ_PHY, 4, 2},
{QLCNIC_CMD_WRITE_PHY, 5, 1},
{QLCNIC_CMD_READ_HW_REG, 4, 1},
{QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
{QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
{QLCNIC_CMD_READ_MAX_MTU, 4, 2},
{QLCNIC_CMD_READ_MAX_LRO, 4, 2},
{QLCNIC_CMD_MAC_ADDRESS, 4, 3},
{QLCNIC_CMD_GET_PCI_INFO, 1, 129},
{QLCNIC_CMD_GET_NIC_INFO, 2, 19},
{QLCNIC_CMD_SET_NIC_INFO, 32, 1},
{QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
{QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
{QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
{QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
{QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
{QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
{QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
{QLCNIC_CMD_CONFIG_PORT, 4, 1},
{QLCNIC_CMD_TEMP_SIZE, 1, 4},
{QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
{QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
{QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
{QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
{QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
{QLCNIC_CMD_CONFIGURE_LED, 2, 1},
{QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
{QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
{QLCNIC_CMD_GET_STATISTICS, 2, 80},
{QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
{QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
{QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
{QLCNIC_CMD_IDC_ACK, 5, 1},
{QLCNIC_CMD_INIT_NIC_FUNC, 3, 1},
{QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
{QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
{QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
{QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
{QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
{QLCNIC_CMD_CONFIG_VPORT, 4, 4},
{QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
{QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
{QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
{QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1},
{QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP, 4, 1},
};
const u32 qlcnic_83xx_ext_reg_tbl[] = {
0x38CC, /* Global Reset */
0x38F0, /* Wildcard */
0x38FC, /* Informant */
0x3038, /* Host MBX ctrl */
0x303C, /* FW MBX ctrl */
0x355C, /* BOOT LOADER ADDRESS REG */
0x3560, /* BOOT LOADER SIZE REG */
0x3564, /* FW IMAGE ADDR REG */
0x1000, /* MBX intr enable */
0x1200, /* Default Intr mask */
0x1204, /* Default Interrupt ID */
0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
0x3784, /* QLC_83XX_IDC_DEV_STATE */
0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
0x378C, /* QLC_83XX_IDC_DRV_ACK */
0x3790, /* QLC_83XX_IDC_CTRL */
0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
0x3798, /* QLC_83XX_IDC_MIN_VERSION */
0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
0x37A0, /* QLC_83XX_IDC_PF_0 */
0x37A4, /* QLC_83XX_IDC_PF_1 */
0x37A8, /* QLC_83XX_IDC_PF_2 */
0x37AC, /* QLC_83XX_IDC_PF_3 */
0x37B0, /* QLC_83XX_IDC_PF_4 */
0x37B4, /* QLC_83XX_IDC_PF_5 */
0x37B8, /* QLC_83XX_IDC_PF_6 */
0x37BC, /* QLC_83XX_IDC_PF_7 */
0x37C0, /* QLC_83XX_IDC_PF_8 */
0x37C4, /* QLC_83XX_IDC_PF_9 */
0x37C8, /* QLC_83XX_IDC_PF_10 */
0x37CC, /* QLC_83XX_IDC_PF_11 */
0x37D0, /* QLC_83XX_IDC_PF_12 */
0x37D4, /* QLC_83XX_IDC_PF_13 */
0x37D8, /* QLC_83XX_IDC_PF_14 */
0x37DC, /* QLC_83XX_IDC_PF_15 */
0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
0x37F0, /* QLC_83XX_DRV_OP_MODE */
0x37F4, /* QLC_83XX_VNIC_STATE */
0x3868, /* QLC_83XX_DRV_LOCK */
0x386C, /* QLC_83XX_DRV_UNLOCK */
0x3504, /* QLC_83XX_DRV_LOCK_ID */
0x34A4, /* QLC_83XX_ASIC_TEMP */
};
const u32 qlcnic_83xx_reg_tbl[] = {
0x34A8, /* PEG_HALT_STAT1 */
0x34AC, /* PEG_HALT_STAT2 */
0x34B0, /* FW_HEARTBEAT */
0x3500, /* FLASH LOCK_ID */
0x3528, /* FW_CAPABILITIES */
0x3538, /* Driver active, DRV_REG0 */
0x3540, /* Device state, DRV_REG1 */
0x3544, /* Driver state, DRV_REG2 */
0x3548, /* Driver scratch, DRV_REG3 */
0x354C, /* Device partition info, DRV_REG4 */
0x3524, /* Driver IDC ver, DRV_REG5 */
0x3550, /* FW_VER_MAJOR */
0x3554, /* FW_VER_MINOR */
0x3558, /* FW_VER_SUB */
0x359C, /* NPAR STATE */
0x35FC, /* FW_IMG_VALID */
0x3650, /* CMD_PEG_STATE */
0x373C, /* RCV_PEG_STATE */
0x37B4, /* ASIC TEMP */
0x356C, /* FW API */
0x3570, /* DRV OP MODE */
0x3850, /* FLASH LOCK */
0x3854, /* FLASH UNLOCK */
};
static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
.read_crb = qlcnic_83xx_read_crb,
.write_crb = qlcnic_83xx_write_crb,
.read_reg = qlcnic_83xx_rd_reg_indirect,
.write_reg = qlcnic_83xx_wrt_reg_indirect,
.get_mac_address = qlcnic_83xx_get_mac_address,
.setup_intr = qlcnic_83xx_setup_intr,
.alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
.mbx_cmd = qlcnic_83xx_issue_cmd,
.get_func_no = qlcnic_83xx_get_func_no,
.api_lock = qlcnic_83xx_cam_lock,
.api_unlock = qlcnic_83xx_cam_unlock,
.add_sysfs = qlcnic_83xx_add_sysfs,
.remove_sysfs = qlcnic_83xx_remove_sysfs,
.process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
.create_rx_ctx = qlcnic_83xx_create_rx_ctx,
.create_tx_ctx = qlcnic_83xx_create_tx_ctx,
.del_rx_ctx = qlcnic_83xx_del_rx_ctx,
.del_tx_ctx = qlcnic_83xx_del_tx_ctx,
.setup_link_event = qlcnic_83xx_setup_link_event,
.get_nic_info = qlcnic_83xx_get_nic_info,
.get_pci_info = qlcnic_83xx_get_pci_info,
.set_nic_info = qlcnic_83xx_set_nic_info,
.change_macvlan = qlcnic_83xx_sre_macaddr_change,
.napi_enable = qlcnic_83xx_napi_enable,
.napi_disable = qlcnic_83xx_napi_disable,
.config_intr_coal = qlcnic_83xx_config_intr_coal,
.config_rss = qlcnic_83xx_config_rss,
.config_hw_lro = qlcnic_83xx_config_hw_lro,
.config_promisc_mode = qlcnic_83xx_nic_set_promisc,
.change_l2_filter = qlcnic_83xx_change_l2_filter,
.get_board_info = qlcnic_83xx_get_port_info,
.set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
.free_mac_list = qlcnic_82xx_free_mac_list,
.io_error_detected = qlcnic_83xx_io_error_detected,
.io_slot_reset = qlcnic_83xx_io_slot_reset,
.io_resume = qlcnic_83xx_io_resume,
.get_beacon_state = qlcnic_83xx_get_beacon_state,
.enable_sds_intr = qlcnic_83xx_enable_sds_intr,
.disable_sds_intr = qlcnic_83xx_disable_sds_intr,
.enable_tx_intr = qlcnic_83xx_enable_tx_intr,
.disable_tx_intr = qlcnic_83xx_disable_tx_intr,
.get_saved_state = qlcnic_83xx_get_saved_state,
.set_saved_state = qlcnic_83xx_set_saved_state,
.cache_tmpl_hdr_values = qlcnic_83xx_cache_tmpl_hdr_values,
.get_cap_size = qlcnic_83xx_get_cap_size,
.set_sys_info = qlcnic_83xx_set_sys_info,
.store_cap_mask = qlcnic_83xx_store_cap_mask,
.encap_rx_offload = qlcnic_83xx_encap_rx_offload,
.encap_tx_offload = qlcnic_83xx_encap_tx_offload,
};
static struct qlcnic_nic_template qlcnic_83xx_ops = {
.config_bridged_mode = qlcnic_config_bridged_mode,
.config_led = qlcnic_config_led,
.request_reset = qlcnic_83xx_idc_request_reset,
.cancel_idc_work = qlcnic_83xx_idc_exit,
.napi_add = qlcnic_83xx_napi_add,
.napi_del = qlcnic_83xx_napi_del,
.config_ipaddr = qlcnic_83xx_config_ipaddr,
.clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
.shutdown = qlcnic_83xx_shutdown,
.resume = qlcnic_83xx_resume,
};
void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
{
ahw->hw_ops = &qlcnic_83xx_hw_ops;
ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
}
int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
{
u32 fw_major, fw_minor, fw_build;
struct pci_dev *pdev = adapter->pdev;
fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
return adapter->fw_version;
}
static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
{
void __iomem *base;
u32 val;
base = adapter->ahw->pci_base0 +
QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
writel(addr, base);
val = readl(base);
if (val != addr)
return -EIO;
return 0;
}
int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
int *err)
{
struct qlcnic_hardware_context *ahw = adapter->ahw;
*err = __qlcnic_set_win_base(adapter, (u32) addr);
if (!*err) {
return QLCRDX(ahw, QLCNIC_WILDCARD);
} else {
dev_err(&adapter->pdev->dev,
"%s failed, addr = 0x%lx\n", __func__, addr);
return -EIO;
}
}
int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
u32 data)
{
int err;
struct qlcnic_hardware_context *ahw = adapter->ahw;
err = __qlcnic_set_win_base(adapter, (u32) addr);
if (!err) {
QLCWRX(ahw, QLCNIC_WILDCARD, data);
return 0;
} else {
dev_err(&adapter->pdev->dev,
"%s failed, addr = 0x%x data = 0x%x\n",
__func__, (int)addr, data);
return err;
}
}
static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter)
{
struct qlcnic_hardware_context *ahw = adapter->ahw;
/* MSI-X enablement failed, use legacy interrupt */
adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
adapter->msix_entries[0].vector = adapter->pdev->irq;
dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
}
static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter)
{
int num_msix;
num_msix = adapter->drv_sds_rings;
/* account for AEN interrupt MSI-X based interrupts */
num_msix += 1;
if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
num_msix += adapter->drv_tx_rings;
return num_msix;
}
int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
{
struct qlcnic_hardware_context *ahw = adapter->ahw;
int err, i, num_msix;
if (adapter->flags & QLCNIC_TSS_RSS) {
err = qlcnic_setup_tss_rss_intr(adapter);
if (err < 0)
return err;
num_msix = ahw->num_msix;
} else {
num_msix = qlcnic_83xx_calculate_msix_vector(adapter);
err = qlcnic_enable_msix(adapter, num_msix);
if (err == -ENOMEM)
return err;
if (adapter->flags & QLCNIC_MSIX_ENABLED) {
num_msix = ahw->num_msix;
} else {
if (qlcnic_sriov_vf_check(adapter))
return -EINVAL;
num_msix = 1;
adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
}
}
/* setup interrupt mapping table for fw */
ahw->intr_tbl =
vzalloc(array_size(num_msix,
sizeof(struct qlcnic_intrpt_config)));
if (!ahw->intr_tbl)
return -ENOMEM;
if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) {
dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n",
ahw->pci_func);
return -EOPNOTSUPP;
}
qlcnic_83xx_enable_legacy(adapter);
}
for (i = 0; i < num_msix; i++) {
if (adapter->flags & QLCNIC_MSIX_ENABLED)
ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
else
ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
ahw->intr_tbl[i].id = i;
ahw->intr_tbl[i].src = 0;
}
return 0;
}
static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
{
writel(0, adapter->tgt_mask_reg);
}
static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
{
if (adapter->tgt_mask_reg)
writel(1, adapter->tgt_mask_reg);
}
static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
*adapter)
{
u32 mask;
/* Mailbox in MSI-x mode and Legacy Interrupt share the same
* source register. We could be here before contexts are created
* and sds_ring->crb_intr_mask has not been initialized, calculate
* BAR offset for Interrupt Source Register
*/
mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
writel(0, adapter->ahw->pci_base0 + mask);
}
void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
{
u32 mask;
mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
writel(1, adapter->ahw->pci_base0 + mask);
QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
}
static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
struct qlcnic_cmd_args *cmd)
{
int i;
if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
return;
for (i = 0; i < cmd->rsp.num; i++)
cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
}
irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
{
u32 intr_val;
struct qlcnic_hardware_context *ahw = adapter->ahw;
int retries = 0;
intr_val = readl(adapter->tgt_status_reg);
if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
return IRQ_NONE;
if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
adapter->stats.spurious_intr++;
return IRQ_NONE;
}
/* The barrier is required to ensure writes to the registers */
wmb();
/* clear the interrupt trigger control register */
writel_relaxed(0, adapter->isr_int_vec);
intr_val = readl(adapter->isr_int_vec);
do {
intr_val = readl(adapter->tgt_status_reg);
if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
break;
retries++;
} while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
(retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
return IRQ_HANDLED;
}
static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
{
mbx->rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
complete(&mbx->completion);
}
static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
{
u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
unsigned long flags;
spin_lock_irqsave(&mbx->aen_lock, flags);
resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
if (!(resp & QLCNIC_SET_OWNER))
goto out;
event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
if (event & QLCNIC_MBX_ASYNC_EVENT) {
__qlcnic_83xx_process_aen(adapter);
} else {
if (mbx->rsp_status != rsp_status)
qlcnic_83xx_notify_mbx_response(mbx);
}
out:
qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
spin_unlock_irqrestore(&mbx->aen_lock, flags);
}
irqreturn_t qlcnic_83xx_intr(int irq, void *data)
{
struct qlcnic_adapter *adapter = data;
struct qlcnic_host_sds_ring *sds_ring;
struct qlcnic_hardware_context *ahw = adapter->ahw;
if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
return IRQ_NONE;
qlcnic_83xx_poll_process_aen(adapter);
if (ahw->diag_test) {
if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
ahw->diag_cnt++;
qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
return IRQ_HANDLED;
}
if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
} else {
sds_ring = &adapter->recv_ctx->sds_rings[0];
napi_schedule(&sds_ring->napi);
}
return IRQ_HANDLED;
}
irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
{
struct qlcnic_host_sds_ring *sds_ring = data;
struct qlcnic_adapter *adapter = sds_ring->adapter;
if (adapter->flags & QLCNIC_MSIX_ENABLED)
goto done;
if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
return IRQ_NONE;
done:
adapter->ahw->diag_cnt++;
qlcnic_enable_sds_intr(adapter, sds_ring);
return IRQ_HANDLED;
}
void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
{
u32 num_msix;
if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
qlcnic_83xx_set_legacy_intr_mask(adapter);
qlcnic_83xx_disable_mbx_intr(adapter);
if (adapter->flags & QLCNIC_MSIX_ENABLED)
num_msix = adapter->ahw->num_msix - 1;
else
num_msix = 0;
msleep(20);
if (adapter->msix_entries) {
synchronize_irq(adapter->msix_entries[num_msix].vector);
free_irq(adapter->msix_entries[num_msix].vector, adapter);
}
}
int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
{
irq_handler_t handler;
u32 val;
int err = 0;
unsigned long flags = 0;
if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
!(adapter->flags & QLCNIC_MSIX_ENABLED))
flags |= IRQF_SHARED;
if (adapter->flags & QLCNIC_MSIX_ENABLED) {
handler = qlcnic_83xx_handle_aen;
val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
if (err) {
dev_err(&adapter->pdev->dev,
"failed to register MBX interrupt\n");
return err;
}
} else {
handler = qlcnic_83xx_intr;
val = adapter->msix_entries[0].vector;
err = request_irq(val, handler, flags, "qlcnic", adapter);
if (err) {
dev_err(&adapter->pdev->dev,
"failed to register INTx interrupt\n");
return err;
}
qlcnic_83xx_clear_legacy_intr_mask(adapter);
}
/* Enable mailbox interrupt */
qlcnic_83xx_enable_mbx_interrupt(adapter);
return err;
}
void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
{
u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
adapter->ahw->pci_func = (val >> 24) & 0xff;
}
int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
{
void __iomem *addr;
u32 val, limit = 0;
struct qlcnic_hardware_context *ahw = adapter->ahw;
addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
do {
val = readl(addr);
if (val) {
/* write the function number to register */
QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
ahw->pci_func);
return 0;
}
usleep_range(1000, 2000);
} while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
return -EIO;
}
void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
{
void __iomem *addr;
u32 val;
struct qlcnic_hardware_context *ahw = adapter->ahw;
addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
val = readl(addr);
}
void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
loff_t offset, size_t size)
{
int ret = 0;
u32 data;
if (qlcnic_api_lock(adapter)) {
dev_err(&adapter->pdev->dev,
"%s: failed to acquire lock. addr offset 0x%x\n",
__func__, (u32)offset);
return;
}
data = QLCRD32(adapter, (u32) offset, &ret);
qlcnic_api_unlock(adapter);
if (ret == -EIO) {
dev_err(&adapter->pdev->dev,
"%s: failed. addr offset 0x%x\n",
__func__, (u32)offset);
return;
}
memcpy(buf, &data, size);
}
void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
loff_t offset, size_t size)
{
u32 data;
memcpy(&data, buf, size);
qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
}
int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
{
struct qlcnic_hardware_context *ahw = adapter->ahw;
int status;
status = qlcnic_83xx_get_port_config(adapter);
if (status) {
dev_err(&adapter->pdev->dev,
"Get Port Info failed\n");
} else {
if (ahw->port_config & QLC_83XX_10G_CAPABLE) {
ahw->port_type = QLCNIC_XGBE;
} else if (ahw->port_config & QLC_83XX_10_CAPABLE ||
ahw->port_config & QLC_83XX_100_CAPABLE ||
ahw->port_config & QLC_83XX_1G_CAPABLE) {
ahw->port_type = QLCNIC_GBE;
} else {
ahw->port_type = QLCNIC_XGBE;
}
if (QLC_83XX_AUTONEG(ahw->port_config))
ahw->link_autoneg = AUTONEG_ENABLE;
}
return status;
}
static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
{
struct qlcnic_hardware_context *ahw = adapter->ahw;
u16 act_pci_fn = ahw->total_nic_func;
u16 count;
ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
if (act_pci_fn <= 2)
count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
act_pci_fn;
else
count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
act_pci_fn;
ahw->max_uc_count = count;
}
void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
{
u32 val;
if (adapter->flags & QLCNIC_MSIX_ENABLED)
val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
else
val = BIT_2;
QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
}
void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
const struct pci_device_id *ent)
{
u32 op_mode, priv_level;
struct qlcnic_hardware_context *ahw = adapter->ahw;
ahw->fw_hal_version = 2;
qlcnic_get_func_no(adapter);
if (qlcnic_sriov_vf_check(adapter)) {
qlcnic_sriov_vf_set_ops(adapter);
return;
}
/* Determine function privilege level */
op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
if (op_mode == QLC_83XX_DEFAULT_OPMODE)
priv_level = QLCNIC_MGMT_FUNC;
else
priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
ahw->pci_func);
if (priv_level == QLCNIC_NON_PRIV_FUNC) {
ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
dev_info(&adapter->pdev->dev,
"HAL Version: %d Non Privileged function\n",
ahw->fw_hal_version);
adapter->nic_ops = &qlcnic_vf_ops;
} else {
if (pci_find_ext_capability(adapter->pdev,
PCI_EXT_CAP_ID_SRIOV))
set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
adapter->nic_ops = &qlcnic_83xx_ops;
}
}
static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
u32 data[]);
static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
u32 data[]);
void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
struct qlcnic_cmd_args *cmd)
{
int i;
if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
return;
dev_info(&adapter->pdev->dev,
"Host MBX regs(%d)\n", cmd->req.num);
for (i = 0; i < cmd->req.num; i++) {
if (i && !(i % 8))
pr_info("\n");
pr_info("%08x ", cmd->req.arg[i]);
}
pr_info("\n");
dev_info(&adapter->pdev->dev,
"FW MBX regs(%d)\n", cmd->rsp.num);
for (i = 0; i < cmd->rsp.num; i++) {
if (i && !(i % 8))
pr_info("\n");
pr_info("%08x ", cmd->rsp.arg[i]);
}
pr_info("\n");
}
static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
struct qlcnic_cmd_args *cmd)
{
struct qlcnic_hardware_context *ahw = adapter->ahw;
int opcode = LSW(cmd->req.arg[0]);
unsigned long max_loops;
max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
for (; max_loops; max_loops--) {
if (atomic_read(&cmd->rsp_status) ==
QLC_83XX_MBX_RESPONSE_ARRIVED)
return;
udelay(1);
}
dev_err(&adapter->pdev->dev,
"%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
__func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
flush_workqueue(ahw->mailbox->work_q);
return;
}
int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
struct qlcnic_cmd_args *cmd)
{
struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
struct qlcnic_hardware_context *ahw = adapter->ahw;
int cmd_type, err, opcode;
unsigned long timeout;
if (!mbx)
return -EIO;
opcode = LSW(cmd->req.arg[0]);
cmd_type = cmd->type;
err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
if (err) {
dev_err(&adapter->pdev->dev,
"%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
__func__, opcode, cmd->type, ahw->pci_func,
ahw->op_mode);
return err;
}
switch (cmd_type) {
case QLC_83XX_MBX_CMD_WAIT:
if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
dev_err(&adapter->pdev->dev,
"%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
__func__, opcode, cmd_type, ahw->pci_func,
ahw->op_mode);
flush_workqueue(mbx->work_q);
}
break;
case QLC_83XX_MBX_CMD_NO_WAIT:
return 0;
case QLC_83XX_MBX_CMD_BUSY_WAIT:
qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
break;
default:
dev_err(&adapter->pdev->dev,
"%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
__func__, opcode, cmd_type, ahw->pci_func,
ahw->op_mode);
qlcnic_83xx_detach_mailbox_work(adapter);
}
return cmd->rsp_opcode;
}
int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
struct qlcnic_adapter *adapter, u32 type)
{
int i, size;
u32 temp;
const struct qlcnic_mailbox_metadata *mbx_tbl;
memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
mbx_tbl = qlcnic_83xx_mbx_tbl;
size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
for (i = 0; i < size; i++) {
if (type == mbx_tbl[i].cmd) {
mbx->op_type = QLC_83XX_FW_MBX_CMD;
mbx->req.num = mbx_tbl[i].in_args;
mbx->rsp.num = mbx_tbl[i].out_args;
mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
GFP_ATOMIC);
if (!mbx->req.arg)
return -ENOMEM;
mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
GFP_ATOMIC);
if (!mbx->rsp.arg) {
kfree(mbx->req.arg);
mbx->req.arg = NULL;
return -ENOMEM;
}
temp = adapter->ahw->fw_hal_version << 29;
mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
mbx->cmd_op = type;
return 0;
}
}
dev_err(&adapter->pdev->dev, "%s: Invalid mailbox command opcode 0x%x\n",
__func__, type);
return -EINVAL;
}
void qlcnic_83xx_idc_aen_work(struct work_struct *work)
{
struct qlcnic_adapter *adapter;
struct qlcnic_cmd_args cmd;
int i, err = 0;
adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
if (err)
return;
for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
err = qlcnic_issue_cmd(adapter, &cmd);
if (err)
dev_info(&adapter->pdev->dev,
"%s: Mailbox IDC ACK failed.\n", __func__);
qlcnic_free_mbx_args(&cmd);
}
static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
u32 data[])
{
dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
QLCNIC_MBX_RSP(data[0]));
clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
return;
}
static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
{
struct qlcnic_hardware_context *ahw = adapter->ahw;
u32 event[QLC_83XX_MBX_AEN_CNT];
int i;
for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
event[i] = readl(QLCNIC_MBX_FW(ahw, i));
switch (QLCNIC_MBX_RSP(event[0])) {
case QLCNIC_MBX_LINK_EVENT:
qlcnic_83xx_handle_link_aen(adapter, event);
break;
case QLCNIC_MBX_COMP_EVENT:
qlcnic_83xx_handle_idc_comp_aen(adapter, event);
break;
case QLCNIC_MBX_REQUEST_EVENT:
for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
queue_delayed_work(adapter->qlcnic_wq,
&adapter->idc_aen_work, 0);
break;
case QLCNIC_MBX_TIME_EXTEND_EVENT:
ahw->extend_lb_time = event[1] >> 8 & 0xf;
break;
case QLCNIC_MBX_BC_EVENT:
qlcnic_sriov_handle_bc_event(adapter, event[1]);
break;
case QLCNIC_MBX_SFP_INSERT_EVENT:
dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
QLCNIC_MBX_RSP(event[0]));
break;
case QLCNIC_MBX_SFP_REMOVE_EVENT:
dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",