This folder contains a sample project for using the ILI9488 library on Zynq-7000 with PS GPIO and PS SPI.
The design was made in Vivado 2023.1 and Vitis 2023.1 and tested on Zybo Z7-20.
Important
If you have Zybo Z7-10, you must change the board to Z7-10 in Vivado in Tools|Settings|General|Project device.
No other changes in the design should be necessary.
Generate the bitstream and export HW (File|Export|Export Hardware, select "Include Bitstream").
Then, in Vitis, you right-click the "system" project in the Explorer, select "Update Hardware Specification" and specify the .xsa file generated by Vivado. With the HW specification updated, you must re-build all projects in the Vitis workspace.
The HW design is very simple.
I selected Pmod JE on the Zybo Z7 to connect the display. JE is a so-called standard Pmod (see details in the Zybo Z7 Reference Manual).
SPI0 of the Zynq is used, and two EMIO GPIO pins are enabled to be used for RST and DC signals.
The two Slices are used solely for "aesthetic purposes", so the RST and DC pins can be scalar pins in the diagram.
Zynq SPI frequency is kept at default 166.67 MHz. The initialization call XSpiPs_SetClkPrescaler(&SpiInstance,XSPIPS_CLK_PRESCALE_8) is used, which sets the SPI clock for the display to 20.83 MHz (== 166,67 / 8).
20.83 MHz is higher than the 20 MHz specified in the ILI9488 datasheet. Nevertheless, my specimen of the display worked well at this frequency.
If you want to be on the safe side, you can set the SPI frequency to 150 MHz in the Zynq-7000 configuration in Vivado. Then, with the factor XSPIPS_CLK_PRESCALE_8, you get the SPI frequency of 18,75 MHz.
