This folder contains a sample project for using the ILI9488 library on Zynq-7000 with PS GPIO and AXI SPI.
The design was made in Vivado 2023.1 and Vitis 2023.1 and tested on Zybo Z7-20.
Important
If you have Zybo Z7-10, you must change the board to Z7-10 in Vivado in Tools|Settings|General|Project device.
No other changes in the design should be necessary.
Generate the bitstream and export HW (File|Export|Export Hardware, select "Include Bitstream").
Then, in Vitis, you right-click the "system" project in the Explorer, select "Update Hardware Specification" and specify the .xsa file generated by Vivado. With the HW specification updated, you must re-build all projects in the Vitis workspace.
I selected Pmod JE on the Zybo Z7 to connect the display. JE is a so-called standard Pmod (see details in the Zybo Z7 Reference Manual).
Two EMIO GPIO pins are enabled to be used for RST and DC signals.
The two Slices are used solely for "aesthetic purposes", so the RST and DC pins can be scalar pins in the diagram.
The AXI Quad SPI IP is connected to Zynq in the usual way via the AXI interconnect. The Processor System Reset IP is needed to synchronize AXI bus reset signals with the 100 MHz clock FCLK_CLK0 generated by the Zynq.
Input ext_spi_clk of the AXI SPI IP is fed with a 40 MHz clock signal from the Clocking Wizzard. The Frequency Ratio of the AXI SPI IP is set to 2. This results in a 20 MHz SPI clock for the display.
