Size of each transaction

[kaustubhcs]

I was wondering what the number of bits each transaction fetches are.
For example, while using the "HBM2_8Gb_x128.ini" when an address (0x7F00) is READ.

Do you receive 8 bits, 32 bits, 128 bits, or 1024 bits of data?

I am assuming since the bus_width is 128 and the number of channels are 8,
We are fetching 128 * 8 = 1024 bits at a time.

Experimentation, making an assumption with 1024-bit fetches, show that the peak bandwidth of HBM2 is 119.203 GB/s.
This seems to be close to the theoretical peak of 128 GB/s.

Also, how do you model sending different addresses to the eight independent channels in the HBM stack.

Should I create eight different Memory controllers, or just one should do it?
Is it recommended to send multiple transactions per cycle to the HBM?

Any help is appreciated.

Thank you,
Kaustubh Shivdikar

[NicolasMeseguer]

A very interesting question. I would like to know on what basis you calculate the theoretical bandwidth of 128 GB/s. If I am not mistaken in HBM2 memory modules the theoretical bandwidth is 256 GB/s.