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I am trying to integrate DRAMsim3 with gem5, and I was able to successfully build gem5 with DRAmsim3.And I can successfully use the full system mode with AtomicSimple CPU.
But when I use the TimingSimple CPU or O3CPU, I can't get into the system.It will stop in the process of entering the system.
I use the following code to use the DRAMsim3 in FS mode.
The gem5 version is 21.0.0.0. My Run Command is:./build/X86/gem5.opt ./configs/example/fs.py -r 3 --restore-with-cpu=TimingSimpleCPU --kernel=vmlinux-5.4.49 --disk-image=x86-ubuntu.img.
Is there any way I can solve this problem?
The text was updated successfully, but these errors were encountered:
I am trying to integrate DRAMsim3 with gem5, and I was able to successfully build gem5 with DRAmsim3.And I can successfully use the full system mode with AtomicSimple CPU.
But when I use the TimingSimple CPU or O3CPU, I can't get into the system.It will stop in the process of entering the system.
I use the following code to use the DRAMsim3 in FS mode.
test_sys.mem_ctrls = [DRAMsim3()]
test_sys.mem_ctrls[0].range = AddrRange("0","2147483648")
test_sys.mem_ctrls[0].configFile = "ext/dramsim3/DRAMsim3/configs/DDR4final.ini"
test_sys.mem_ctrls[0].port = test_sys.membus.mem_side_ports
The gem5 version is 21.0.0.0. My Run Command is:./build/X86/gem5.opt ./configs/example/fs.py -r 3 --restore-with-cpu=TimingSimpleCPU --kernel=vmlinux-5.4.49 --disk-image=x86-ubuntu.img.
Is there any way I can solve this problem?
The text was updated successfully, but these errors were encountered: