diff --git a/build.sbt b/build.sbt index 9a98c8f4c..c9fca5ac8 100644 --- a/build.sbt +++ b/build.sbt @@ -4,7 +4,7 @@ organization := "edu.berkeley.cs" name := "chiseltest" // we keep in sync with chisel version names -version := "5.0-SNAPSHOT" +version := "6.0-SNAPSHOT" scalaVersion := "2.13.10" @@ -50,8 +50,8 @@ publishTo := { // Provide a managed dependency on X if -DXVersion="" is supplied on the command line. val defaultVersions = Map( - "chisel3" -> "5.0.0", - "firrtl" -> "5.0.0", + "chisel3" -> "6.0.0-M2", + "firrtl" -> "6.0-SNAPSHOT", ) scalacOptions ++= Seq( @@ -72,7 +72,7 @@ scalacOptions ++= Seq( libraryDependencies ++= Seq( "org.chipsalliance" %% "chisel" % defaultVersions("chisel3"), - "edu.berkeley.cs" %% "firrtl" % defaultVersions("firrtl"), + "edu.berkeley.cs" %% "firrtl2" % defaultVersions("firrtl"), "org.scalatest" %% "scalatest" % "3.2.15", "com.lihaoyi" %% "utest" % "0.8.1", "net.java.dev.jna" % "jna" % "5.13.0", diff --git a/src/main/scala/chiseltest/simulator/ChiselBridge.scala b/src/main/scala/chiseltest/simulator/ChiselBridge.scala index 4f6a88e7c..e6ecad50e 100644 --- a/src/main/scala/chiseltest/simulator/ChiselBridge.scala +++ b/src/main/scala/chiseltest/simulator/ChiselBridge.scala @@ -221,13 +221,18 @@ private object ChiselBridge { case Connect(info, loc, expr) => firrtl2.ir.Connect(convert(info), convert(loc), convert(expr)) case Conditionally(info, pred, conseq, alt) => firrtl2.ir.Conditionally(convert(info), convert(pred), convert(conseq), convert(alt)) - case EmptyStmt => firrtl2.ir.EmptyStmt - case Block(stmts) => firrtl2.ir.Block(stmts.map(convert)) - case DefWire(info, name, tpe) => firrtl2.ir.DefWire(convert(info), name, convert(tpe)) - case DefRegister(info, name, tpe, clock, reset, init) => + case EmptyStmt => firrtl2.ir.EmptyStmt + case Block(stmts) => firrtl2.ir.Block(stmts.map(convert)) + case DefWire(info, name, tpe) => firrtl2.ir.DefWire(convert(info), name, convert(tpe)) + case DefRegister(info, name, tpe, clock) => + // default is a self reset with a zero reset signal + val reset = firrtl2.Utils.zero + val firrtl2Tpe = convert(tpe) + val init = firrtl2.ir.Reference(name, firrtl2Tpe, firrtl2.RegKind, firrtl2.SourceFlow) + firrtl2.ir.DefRegister(convert(info), name, firrtl2Tpe, convert(clock), reset, init) + case DefRegisterWithReset(info, name, tpe, clock, reset, init) => firrtl2.ir.DefRegister(convert(info), name, convert(tpe), convert(clock), convert(reset), convert(init)) case DefInstance(info, name, module, tpe) => firrtl2.ir.DefInstance(convert(info), name, module, convert(tpe)) - case PartialConnect(info, loc, expr) => firrtl2.ir.PartialConnect(convert(info), convert(loc), convert(expr)) case Attach(info, exprs) => firrtl2.ir.Attach(convert(info), exprs.map(convert)) case s: Stop => firrtl2.ir.Stop(convert(s.info), s.ret, convert(s.clk), convert(s.en), name = s.name) case p: Print => diff --git a/src/test/scala/chiseltest/iotesters/VecFillSpec.scala b/src/test/scala/chiseltest/iotesters/VecFillSpec.scala index 306e03d66..6b67cbb77 100644 --- a/src/test/scala/chiseltest/iotesters/VecFillSpec.scala +++ b/src/test/scala/chiseltest/iotesters/VecFillSpec.scala @@ -8,7 +8,7 @@ import chiseltest._ class VF extends Module { val io = IO(new Bundle { - val addr = Input(UInt(8.W)) + val addr = Input(UInt(4.W)) val value = Output(UInt(8.W)) }) diff --git a/src/test/scala/chiseltest/tests/ChiselEnumTest.scala b/src/test/scala/chiseltest/tests/ChiselEnumTest.scala index 4a60e4a19..d722e6d72 100644 --- a/src/test/scala/chiseltest/tests/ChiselEnumTest.scala +++ b/src/test/scala/chiseltest/tests/ChiselEnumTest.scala @@ -36,7 +36,9 @@ class ChiselEnumTest extends AnyFlatSpec with ChiselScalatestTester { val in = Input(UInt(2.W)) val out = Output(EnumExample()) }) - io.out := io.in.asTypeOf(chiselTypeOf(io.out)) + val (value, safe) = EnumExample.safe(io.in) + chisel3.assert(safe) + io.out := value }) { c => c.io.in.poke(0.U) c.io.out.expect(EnumExample.e0)