How does the system bus connect modules together?

[OrkunAliOzkan]

Hello! :)

I am reaching out to seek guidance on the TileLink interconnect in chipyard, specifically conserning the connection between the L2 banks to the core (in my case rocket). My aim for starting this discussion is to have a place where extensive details regarding how other hardware modules connect up to the system-bus (with code snippets in Chipyard as a point of reference ideally), such that beginners like myself can review and understand. The context in which I ask this is to better understand the source code relating the L2 banks and the system-bus, how those two modules connect, as well as how they connect up to the rocket-chip. Through this discussion I would really like to have the knowledge base needed to directly connect the inclusive-cache to the Rocket-chip in the chipsalliance rocket-chip generator.

I have reviewed the source code for the inclsuive-cache and I don't see where the L2 cache banks are getting connected to the sbus, I have review documentation explaining the various different TileLink nodes operate and when to invoke them, though I am left with more questions than answers.

What I find most useful would be code snippets from the chipyard sourceode which show the points where the L2 gets connected to the sbus, why that is so (or links to respective docs which cover it) if there are details in the matter of TileLink which I may be missing (I do understand that TileLink generates these connections during compile time so connections aren't so explicitly mentioned!) and any discussion around that point really.

I am new to this repo and while it may be trivial to some, it is still quite novel and challenging for me to grasp. I would sincerely appreciate any help in getting a clearer understanding.

Have a lovely day :)
Orkun