-
Notifications
You must be signed in to change notification settings - Fork 0
/
harness.jsim
154 lines (129 loc) · 4.04 KB
/
harness.jsim
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
// Design Project w/ beta implemention as described in lab handouts
.include "projcheckoff.jsim"
// matches .subckt above w/ IRQ tied to ground
Xbeta clk reset 0 ia[31:0] id[31:0] ma[31:0] moe mrd[31:0] wr mwd[31:0] beta
// your memory must also be called Xmem (so the checkoff code can find it!) but
// can have a different number of ports. It should however be initialized with
// the contents shown below -- the benchmark suite. A file containing these
// values can be found at /mit/6.004/jsim/projcheckoff.bin.
Xmwd wr#32 mwd[31:0] md[31:0] tristate
Xmrd md[31:0] mrd[31:0] cnxn
Xmem
+ vdd 0 0 ia[11:2] id[31:0]
+ moe clk wr ma[11:2] md[31:0]
+ $memory width=32 nlocations=1024
+ file="projcheckoff.bin"
// Run the simulation for 1205 cycles. Your design might require more or less
// cycles depending on how it executes instructions. Run only as long as necessary
// to complete the benchmark since the ending simulation time is used to compute
// your circuit?s Benmark
Vreset reset 0 pwl(0ns 3.3v, 9ns 3.3v, 9.1ns 0v)
// BENMARK:
// 1e-10/([area]e-12*[ns]e-9)
// BMK = 46.74 @ 306114 mc2
Vclk clk 0 pulse(3.3,0,3.01ns,.01ns,.01ns,3.01ns)
.tran 6989ns
// BMK = 45.02 @ 310414 mc2
//Vclk clk 0 pulse(3.3,0,3.42ns,.01ns,.01ns,3.42ns)
//.tran 7155ns
// BMK = 43.75 @ 310371 mc2
//Vclk clk 0 pulse(3.3,0,3.52ns,.01ns,.01ns,3.52ns)
//.tran 7364ns
// BMK = 40.18 @ 293789 mc2
//Vclk clk 0 pulse(3.3,0,4.23ns,.01ns,.01ns,4.23ns)
//.tran 8472ns
// BMK = 39.47 @ 299054 mc2
//Vclk clk 0 pulse(3.3,0,4.23ns,.01ns,.01ns,4.23ns)
//.tran 8472ns
// BMK = 36.69 @ 288499 mc2
//Vclk clk 0 pulse(3.3,0,4.23ns,.01ns,.01ns,4.23ns)
//.tran 9448ns
// BMK = 34.90 @ 285489 mc2
//Vclk clk 0 pulse(3.3,0,4.49ns,.01ns,.01ns,4.49ns)
//.tran 10036ns
// BMK = 28.24 @ 280753 mc2
//Vclk clk 0 pulse(3.3,0,5.65ns,.01ns,.01ns,5.65ns)
//.tran 12612ns
// BMK = 24.97 @ 276387 mc2
//Vclk clk 0 pulse(3.3,0,4ns,.01ns,.01ns,7.67ns)
//.tran 14489ns
// BMK = 22.36 @ 308659 mc2
//Vclk clk 0 pulse(3.3,0,4ns,.01ns,.01ns,7.67ns)
//.tran 14489ns
.plot clk
//.plot reset
//.plot Xbeta.Xbeta1.annul
.plot Xbeta.Xbeta1.stall
//* ops and registers *
.plot ia[31:0]
.plot betaop(Xbeta.if_ir[31:26])
.plot betaop(Xbeta.exe_ir[31:26])
//.plot reg(Xbeta.Xbeta2.Xregfile.ra[4:0])
//.plot reg(Xbeta.Xbeta2.Xregfile.rb[4:0])
//.plot reg(Xbeta.Xbeta2.Xregfile.rc[4:0])
.plot betaop(Xbeta.mem_ir[31:26])
*/
/* all registers *
.plot ia[31:0]
.plot betaop(Xbeta.if_ir[31:26])
.plot betaop(Xbeta.exe_ir[31:26])
.plot betaop(Xbeta.mem_ir[31:26])
.plot Xbeta.Xbeta1.Xpc.d[31:2]
.plot Xbeta.st_pc[31:2]
.plot Xbeta.st_ir[31:0]
.plot Xbeta.exe_pc[31:2]
.plot Xbeta.exe_wd[31:0]
.plot Xbeta.exe_alu[31:0]
.plot Xbeta.an_exe_ir[31:0]
.plot Xbeta.wdata[31:0]
*/
.plot Xbeta.ma[31:0]
.plot Xbeta.moe
.plot Xbeta.mrd[31:0]
.plot Xbeta.Xbeta3.wdsel[1:0]
.plot Xbeta.wdata[31:0]
/*
.plot Xbeta.Xbeta1.Xbr.z
.plot Xbeta.Xbeta1.Xbr.br_miss
.plot Xbeta.Xbeta1.Xbr.br_annul
.plot Xbeta.Xbeta1.annul
.plot Xbeta.Xbeta1.id[31:0]
.plot Xbeta.if_ir[31:0]
.plot Xbeta.st_ir[31:0]
*/
/*
.plot Xbeta.Xbeta1.Xpc.pc[31:2]
.plot Xbeta.Xbeta1.Xpc.exe_pcr[31:2]
.plot Xbeta.Xbeta1.Xpc.z
.plot Xbeta.Xbeta1.Xpc.br_pc[31:2]
.plot Xbeta.Xbeta1.Xpc.pcsel[1:0]
.plot Xbeta.Xbeta1.Xpc.__d[31:2]
.plot Xbeta.Xbeta1.Xpc.stall
.plot Xbeta.Xbeta1.Xpc._d[31:2]
.plot Xbeta.Xbeta1.Xpc.d[31:2]
*/
/*
//.plot Xbeta.Xbeta2.alufn[5:0]
//.plot Xbeta.Xbeta2.b[31:0]
//.plot Xbeta.Xbeta2.asel
//.plot Xbeta.Xbeta2.Xregfile.ra[4:0]
//.plot Xbeta.Xbeta2.Xregfile.adata[31:0]
//.plot Xbeta.Xbeta3.Xmemctl._wdsel[1:0]
//.plot Xbeta.Xbeta3.Xmemctl.irq
//.plot Xbeta.Xbeta3.wdsel[1:0]
//.plot Xbeta.Xbeta3.alu[31:0]
//.plot Xbeta.Xbeta3.Xmemctl._werf
//.plot Xbeta.Xbeta2.Xregfile.Xbypctl.werf
//.plot Xbeta.Xbeta2.Xregfile.Xbypctl.ra_match
//.plot Xbeta.Xbeta2.Xregfile.Xbypctl.ra_not31
//.plot Xbeta.Xbeta2.Xregfile.bypa
//.plot Xbeta.Xbeta2.Xregfile.wdata[31:0]
.plot Xbeta.Xbeta2.Xregfile.yadata[31:0]
//.plot Xbeta.Xbeta2.Xregfile.r31a
.plot Xbeta.Xbeta2.radata[31:0]
.plot Xbeta.Xbeta2.a[31:0]
.plot Xbeta.Xbeta2.b[31:0]
.plot Xbeta.Xbeta2.alu[31:0]
//.plot Xbeta.Xbeta2.pcr[31:2]
.plot Xbeta.exe_alu[31:0]
*/